Circuits and Methods Providing High-Speed Data Link with Equalizer

Abstract

Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but- for the equalizer.

What is claimed is: 
     
         1 . A circuit comprising:
 a data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to the characteristic impedance of the transmission line, the termination impedance of the data receiver being higher than the characteristic impedance of the transmission line; and   an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce Resistance Capacitance (RC) attenuation distortion.   
     
     
         2 . The circuit of  claim 1 , wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the impedance of the transmission line. 
     
     
         3 . The circuit of  claim 1 , wherein the data receiver is included in a Double Data Rate (DDR) memory device. 
     
     
         4 . The circuit of  claim 1 , wherein the data receiver is included in a system on a chip. 
     
     
         5 . The circuit of  claim 1 , wherein the termination impedance of the data receiver is adjustable. 
     
     
         6 . The circuit of  claim 5 , wherein the termination impedance is provided by an impedance element having a plurality of selectable resistance elements. 
     
     
         7 . The circuit of  claim 1 , wherein a mismatch ratio of the termination impedance to the characteristic impedance of the transmission line is between 2:1 and 3:1. 
     
     
         8 . The circuit of  claim 1 , wherein the data receiver is configured to accept a variable data rate for the channel-transmitted data signal. 
     
     
         9 . The circuit of  claim 1 , further comprising a transmitter in communication with the transmission line, the transmitter configured to originate the channel-transmitted data signal, wherein the transmitter includes an adjustable termination impedance. 
     
     
         10 . The circuit of  claim 1 , further comprising a flip-flop configured to capture bits of data from the receiver. 
     
     
         11 . A system comprising:
 means for receiving a channel-transmitted data signal from a transmission line, the means for receiving having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line, wherein the termination impedance of the means for receiving is higher than the characteristic impedance of the transmission line by a ratio of at least 2:1;   means for reshaping the channel-transmitted data signal by providing gain to portions of the channel-transmitted data signal attenuated by the transmission line and the means for receiving; and   means for capturing the channel-transmitted data signal subsequent to reshaping the channel-transmitted data signal.   
     
     
         12 . The system of  claim 11 , wherein the means for receiving is included in a Double Data Rate (DDR) memory element. 
     
     
         13 . The system of  claim 11 , wherein the means for receiving comprises an amplifier. 
     
     
         14 . The system of  claim 11 , wherein the termination impedance of the means for receiving is adjustable. 
     
     
         15 . The system of  claim 14 , wherein the termination impedance is provided by an impedance element having a plurality of selectable resistance elements. 
     
     
         16 . The system of  claim 11 , wherein a mismatch ratio of the termination impedance of the means for receiving to the characteristic impedance of the transmission line is between 2:1 and 3:1. 
     
     
         17 . The system of  claim 11 , wherein the means for receiving is configured to accept a variable data rate for the channel-transmitted data signal.