Inventor · disambiguated record
Luverne Ray Peterson
Also filed as: PETERSON LUVERNE · PETERSON LUVERNE R · PETERSON LUVERNE RAY
34 granted patents·2 pending applications·354 citations·filing 1981–2018
97Inventor score
Top patents by PatentIndex Score
36 records- 0191US9977078B2Systems and methods for wafer-level loopback testQUALCOMM INC·Filed 2014·Granted May 22, 2018·8 cites·15 claims
- 0290US8596864B2Digital output temperature sensor and method of temperature sensingPETERSON LUVERNE R·Filed 2011·Granted Dec 3, 2013·12 cites·21 claims
- 0390US8262286B2Digital output temperature sensorPETERSON LUVERNE R·Filed 2008·Granted Sep 11, 2012·32 cites·16 claims
- 0489US9536593B1Low power receiver with wide input voltage rangeQUALCOMM INC·Filed 2016·Granted Jan 3, 2017·10 cites·22 claims
- 0589US5898242ASelf-calibrating clock circuit employing a continuously variable delay module in a feedback loopUNISYS CORP·Filed 1993·Granted Apr 27, 1999·58 cites·10 claims
- 0686US9614703B2Circuits and methods providing high-speed data link with equalizerQUALCOMM INC·Filed 2015·Granted Apr 4, 2017·6 cites·28 claims
- 0785US7271751B2Digital BIST test scheme for ADC/DAC circuitsTOSHIBA AMERICA ELECTRONIC·Filed 2006·Granted Sep 18, 2007·27 cites·20 claims
- 0884US10114074B2Systems and methods for wafer-level loopback testQUALCOMM INC·Filed 2018·Granted Oct 30, 2018·2 cites·20 claims
- 0984US9245870B1Systems and methods for providing data channels at a die-to-die interfaceQUALCOMM INC·Filed 2014·Granted Jan 26, 2016·7 cites·30 claims
- 1077US6385070B1Content Addressable Memory array, cell, and method using 5-transistor compare circuit and avoiding crowbar currentTALITY L P·Filed 2001·Granted May 7, 2002·27 cites·16 claims
- 1175US9350339B2Systems and methods for clock distribution in a die-to-die interfaceQUALCOMM INC·Filed 2014·Granted May 24, 2016·3 cites·12 claims
- 1274US4508977ARe-programmable PLABURROUGHS CORP·Filed 1983·Granted Apr 2, 1985·19 cites·13 claims
- 1373US10424921B2Die-to-die interface configuration and methods of use thereofQUALCOMM INC·Filed 2017·Granted Sep 24, 2019·2 cites·25 claims
- 1468US9825626B2Programmable high-speed equalizer and related methodQUALCOMM INC·Filed 2015·Granted Nov 21, 2017·2 cites·25 claims
- 1565US6400592B1Content addressable memory cell and design methodologyCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Jun 4, 2002·14 cites·44 claims
- 1665US6331942B1Content addressable memory cell and design methodology utilizing grounding circuitryTALITY L P·Filed 2000·Granted Dec 18, 2001·14 cites·46 claims
- 1765US4719627AMemory system employing a low DC power gate array for error correctionUNISYS CORP·Filed 1986·Granted Jan 12, 1988·43 cites·8 claims
- 1859US7429882B2AC-DC input bufferTOSHIBA AMERICA ELECTRONIC·Filed 2006·Granted Sep 30, 2008·3 cites·17 claims
- 1957US6381162B1Circuitry and method for controlling current surge on rails of parallel-pulldown-match-detect-type content addressable memory arraysTALITY L P·Filed 2001·Granted Apr 30, 2002·10 cites·17 claims
- 2056US7893731B2AC/DC input bufferTOSHIBA AMERICA ELECTRONIC·Filed 2008·Granted Feb 22, 2011·2 cites·20 claims
- 2156US6348814B1Constant edge output buffer circuit and methodCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Feb 19, 2002·7 cites·12 claims
- 2254US4376986ADouble Lambda diode memory cellBURROUGHS CORP·Filed 1981·Granted Mar 15, 1983·9 cites·9 claims
- 2351US9654090B2Systems and methods for clock distribution in a die-to-die interfaceQUALCOMM INC·Filed 2016·Granted May 16, 2017·0 cites·17 claims
- 2448US2017134191A1Circuits and Methods Providing High-Speed Data Link with EqualizerQUALCOMM INC·Filed 2017·Application pending·0 cites
- 2544US10044342B2Delay line for one shot pre-emphasisQUALCOMM INC·Filed 2016·Granted Aug 7, 2018·0 cites·26 claims
- 2644US4942398ADigital signal translator having compensation for P-channel and N-channel threshold voltage shiftsUNISYS CORP·Filed 1989·Granted Jul 17, 1990·6 cites·12 claims
- 2743US9698782B1Systems and methods to provide charge sharing at a transmit buffer circuitQUALCOMM INC·Filed 2016·Granted Jul 4, 2017·0 cites·30 claims
- 2841US9859888B2Transmitter with feedback terminated preemphasisQUALCOMM INC·Filed 2016·Granted Jan 2, 2018·0 cites·20 claims
- 2940US5345113AControl module for reducing ringing in digital signals on a transmission lineUNISYS CORP·Filed 1993·Granted Sep 6, 1994·5 cites·13 claims
- 3036US5146424ADigital adder having a high-speed low-capacitance carry bypass signal pathUNISYS CORP·Filed 1991·Granted Sep 8, 1992·8 cites·17 claims
- 3136US4839848AFast multiplier circuit incorporating parallel arrays of two-bit and three-bit addersUNISYS CORP·Filed 1987·Granted Jun 13, 1989·12 cites·10 claims
- 3232US5166660ARandom access compare arrayUNISYS CORP·Filed 1991·Granted Nov 24, 1992·4 cites·11 claims
- 3332US2016285453A1Driver using pull-up nmos transistorQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3431US4517662AHigh-speed, compact magnetic bubble stretcherBURROUGHS CORP·Filed 1983·Granted May 14, 1985·0 cites·10 claims
- 3531US4511995ADetector-dummy detector combination which is integrated as a single element of reduced sizeBURROUGHS CORP·Filed 1983·Granted Apr 16, 1985·0 cites·11 claims
- 3622US4698812AMemory system employing a zero DC power gate array for error correctionUNISYS CORP·Filed 1986·Granted Oct 6, 1987·2 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →