Digital BIST test scheme for ADC/DAC circuits

Abstract

A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and ADCs may be tested at the highest clock frequency allowed in the specification, shortening test time. The test circuits required for this test scheme comprise cell logic two multiplexer cells and an internal Analog Test Bus. This scheme is extendable to the testing of many DACs and ADCs on the same IC. The number of DACs and ADCs need not be equal. Furthermore, the DACs may have more (or less) bits (addresses) than the ADCs. An ADC may be tested with more than one DAC or vice versa to determine which cell is at fault if a test fails.

1. An apparatus, comprising:
 a digital to analog converter having an input and an output, the digital to analog converter responsive to produce an analog output signal at the output based on a digital signal received at the input; 
 a test bus; 
 a digital to analog converter pad; 
 a first controllable switching device operable to switch the analog output signal to one of the group consisting of the test bus and the digital to analog converter pad; 
 an analog to digital converter having an input and an output; 
 an analog to digital converter pad; 
 a second controllable switching device operable to couple one of the test bus and the analog to digital converter pad to the input of the analog to digital converter; and 
 a third controllable switching device coupled between the test bus and a ground, the third controllable switching device responsive to couple the test bus to the ground during a predetermined state. 
 
   
   
     2. An apparatus according to  claim 1 , wherein the predetermined state is when no testing is occurring. 
   
   
     3. An apparatus according to  claim 1 , wherein the test bus is an analog bus. 
   
   
     4. An apparatus according to  claim 1 , wherein the first controllable switching device and the second controllable switching device are analog multiplexers. 
   
   
     5. An apparatus according to  claim 1 , further comprising:
 a digital to analog test logic coupled to the digital to analog converter; 
 an analog to digital test logic coupled to the analog to digital converter; and 
 a test multiplexer coupled to the digital to analog test logic, analog to digital test logic, the first controllable switching device, and the second controllable switching device; 
 wherein the test multiplexer is operable to control the operation of the first controllable switching device and the second controllable switching device to couple the output of digital to analog converter and the input of the analog to digital converter to the test bus while a test is being performed. 
 
   
   
     6. An apparatus according to  claim 5 , further comprising:
 the test multiplexer is operable to receive test data from the digital to analog test logic and forward the test data to the analog to digital test logic; and 
 the analog to digital test logic is operable to compare the output of the analog to digital converter with the test data. 
 
   
   
     7. An apparatus according to  claim 6 , wherein the analog to digital test logic determines the test is successful based on one of the group consisting of the output of the analog to digital converter is equal to the test data, the output of the analog to digital converter is one bit less than the test data, and the output of the analog to digital converter is one bit greater than the test data. 
   
   
     8. An apparatus, comprising:
 a digital to analog converter having an input and an output, the digital to analog converter responsive to produce an analog output signal at the output based on a digital signal received at the input; 
 a test bus; 
 a digital to analog converter pad; 
 a first controllable switching device operable to switch the analog output signal to one of the group consisting of the test bus and the digital to analog converter pad; 
 an analog to digital converter having an input and an output; 
 an analog to digital converter pad; 
 a second controllable switching device operable to couple one of the test bus and the analog to digital converter pad to the input of the analog to digital converter; 
 a second digital to analog converter having input and an output, the digital to analog converter responsive to produce an analog output signal at the output based on a digital signal received at the input; 
 a second digital to analog converter pad; 
 a third controllable switching device operable to switch the analog output signal from the second digital to analog converter to one of the group consisting of the test bus and the second digital to analog converter pad; 
 a second analog to digital converter pad; 
 a second controllable switching device operable to couple one of the test bus and the analog to digital converter pad to the input of the analog to digital converter; 
 a second analog to digital converter having an input and an output; 
 a fourth controllable switching device operable to couple one of the test bus and the second analog to digital converter pad to the input of the second analog to digital converter; 
 a test multiplexer coupled to the first controllable switching device, the second controllable switching device, the third controllable switching device, and the fourth controllable switching device, wherein the test multiplexer is operable to control the operation of the first controllable switching device, the second controllable switching device, the third controllable switching device and the fourth controllable switching device to route the output of one of the group consisting of the first digital to analog converter and the second digital to analog converter to the test bus, and to route the output of one of the group consisting of the first analog to digital converter and the second analog to digital converter to the test bus while a test is being performed; and 
 a fifth controllable switching device coupled between the test bus and a ground, wherein the fifth controllable switching device is responsive to signals from the test multiplexer to couple the test bus to ground while in a normal, non-test mode. 
 
   
   
     9. An apparatus according to  claim 8 , further comprising:
 the test multiplexer is operable to couple not more than one of the group consisting of the first digital to analog converter and the second digital to analog converter to the test bus at any time; and 
 the test multiplexer is operable to couple not more than one of the group consisting of the first analog to digital converter and the second analog to digital converter to the test bus at any time. 
 
   
   
     10. An apparatus, comprising:
 a digital to analog converter having an input and an output, the digital to analog converter responsive to produce an analog output signal at the output based on a digital signal received at the input; 
 a test bus; 
 a digital to analog converter pad; 
 a first controllable switching device operable to switch the analog output signal to one of the group consisting of the test bus and the digital to analog converter pad; 
 an analog to digital converter having an input and an output; 
 an analog to digital converter pad; 
 a second controllable switching device operable to couple one of the test bus and the analog to digital converter pad to the input of the analog to digital converter; 
 a second digital to analog converter having input and an output, the digital to analog converter responsive to produce an analog output signal at the output based on a digital signal received at the input; 
 a second digital to analog converter pad; 
 a third controllable switching device operable to switch the analog output signal from the second digital to analog converter to one of the group consisting of the test bus and the second digital to analog converter pad; 
 a second analog to digital converter having an input and an output; 
 a second analog to digital converter pad; 
 a fourth controllable switching device operable to couple one of the test bus and the second analog to digital converter pad to the input of the second analog to digital converter; 
 a first digital to analog test logic associated with the first digital to analog converter; 
 a first analog to digital test logic associated with the first analog to digital converter; 
 a second digital to analog test logic associated with the second digital to analog converter; 
 a second analog to digital test logic associated with the second analog to digital converter; and 
 a test multiplexer coupled to the first digital to analog test logic, second digital to analog test logic, first analog to digital test logic, second analog to digital test logic, the first controllable switching device, and the second controllable switching device, the third controllable switching device, 
 wherein the test multiplexer is operable to control the operation of the first controllable switching device, the second controllable switching device, the third controllable switching device and the fourth controllable switching device to couple a selected one of the group consisting of the output of the first digital to analog converter and the output of the second digital to analog converter to the test bus and to couple a selected one of the group consisting of the input of the first analog to digital converter and the input of the second analog to digital converter to the test bus while a test is being performed. 
 
   
   
     11. An apparatus according to  claim 10 , further comprising:
 the test multiplexer is operable to receive test data from the test logic associated with the selected one of the group consisting of the first digital to analog converter and the second digital to analog converter and forward the test data to the test logic associated with the selected one of the group consisting of the first analog to digital converter and the second analog to digital converter; and 
 wherein the test logic is operable to compare the output of selected one of the group consisting of the first analog to digital converter and the second analog to digital converter with the test data. 
 
   
   
     12. An apparatus according to  claim 11 , wherein the analog to digital test logic determines a test is successful based on one of the group consisting of the output of the selected one of the group consisting of the first analog to digital converter and the second analog to digital converter is equal to the test data, the output of the selected one of the group consisting of the first analog to digital converter and the second analog to digital converter is one bit less than the test data, and the output of selected one of the group consisting of the first analog to digital converter and the second analog to digital converter is one bit greater than the test data. 
   
   
     13. An apparatus according to  claim 11 , further comprising the associated analog to digital test logic selects a predetermined number of most significant bits from the test data and compares them to corresponding most significant bits from the output of the selected one of the group consisting of the first analog to digital converter and the second analog to digital converter. 
   
   
     14. An apparatus according to  claim 13 , the associated analog to digital test logic is configured to cycle through least significant bits lower than the predetermined number of most significant bits, wherein the associated analog to digital test logic determines the test is successful based on the predetermined number of most significant bits of the output of the selected one of the group consisting of the first analog to digital converter and the second analog to digital converter changing by not more than one bit throughout the cycle. 
   
   
     15. An apparatus, comprising
 a plurality of digital to analog converters; 
 a plurality of analog to digital converts; 
 a test bus; 
 means for coupling not more than one of the plurality of digital to analog converters to not more than one of the plurality of analog to digital converters via the test bus; 
 means for applying a test signal to the one of the plurality of digital to analog converters; 
 means for comparing an output from the not more than one of the analog to digital converters with the test signal; and 
 means for coupling the test bus to a ground when no testing is in progress. 
 
   
   
     16. An apparatus according to  claim 15 , wherein the means for comparing determines a successful test based on one of the group consisting of output from the not more than one of the analog to digital converters equals the test signal, the output from the not more than one of the analog to digital converters is not more than one least significant bit less than the test signal, and the output from the not more than one of the analog to digital converters is not more than one least significant bit than the test signal. 
   
   
     17. An apparatus, comprising:
 a plurality of digital to analog converters; 
 a plurality of analog to digital converts; 
 a test bus; 
 means for coupling not more than one of the plurality of digital to analog converters to not more than one of the plurality of analog to digital converters via the test bus; 
 means for applying a test signal to one of the plurality of digital to analog converters; and 
 means for comparing an output from the one of the analog to digital converters with the test signal, 
 wherein the means for comparing compares a predetermined number of most significant digits from the output from the not more than one of the analog to digital converters with the test signal, and the means for comparing cycles through all of the least significant bits that are not in the predetermined number of most significant bits and determines a test is successful based on the predetermined number of most significant bits of the output of the selected one of the group consisting of the first analog to digital converter and the second analog to digital converter changing by not more than one bit throughout the cycle. 
 
   
   
     18. A method, comprising
 coupling a one of a plurality of digital to analog converters a one of a plurality of analog to digital converters via a test bus; 
 applying a test signal to the one of the plurality of digital to analog converters; 
 comparing an output from the one of the analog to digital converters with the test signal; and 
 coupling the test bus to a ground when no testing is in progress. 
 
   
   
     19. A method according to  claim 18 , further comprising determining a test is successful responsive to the comparing determining one of the group consisting of the output from the not more than one analog to digital converter equals the test signal, the output from the not more than one analog to digital converter is not more than one least significant bit less than the test signal, and the output from the not more than one analog to digital converters is not more than one least significant bit less than the test signal. 
   
   
     20. A method, comprising:
 coupling a one of a plurality of digital to analog converters to a one of a plurality of analog to digital converters via a test bus; 
 applying a test signal to the one of the plurality of digital to analog converters; and 
 comparing an output from the one of the analog to digital converters with the test signal, 
 wherein the means for comparing compares a predetermined number of most significant digits from the output from the not more than one of the analog to digital converters with the test signal, and the means for comparing cycles through all of the least significant bits that are not in the predetermined number of most significant bits and determines a test is successful based on the predetermined number of most significant bits of the output of the selected one of the group consisting of the first analog to digital converter and the second analog to digital converter changing by not more than one bit throughout the cycle.