Deep trench capacitor with scallop profile

Abstract

The present disclosure relates to an integrated chip having a deep trench capacitor with serrated sidewalls defining curved depressions, and a method of formation. In some embodiments, the integrated chip includes a substrate having a trench with serrated sidewalls defining a plurality of curved depressions. A layer of dielectric material conformally lines the serrated sidewalls, and a layer of conductive material is arranged within the trench and is separated from the substrate by the layer of dielectric material. The layer of dielectric material is configured as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate. The serrated sidewalls of the layer of conductive material increase a surface area of exterior surfaces of the layer of conductive material, thereby increasing a capacitance of the capacitor per unit of depth

What is claimed is: 
     
         1 . An integrated chip, comprising:
 a substrate having a trench with serrated sidewalls defining a plurality of curved depressions;   a layer of dielectric material conformally lining the serrated sidewalls; and   a layer of conductive material separated from the substrate by the layer of dielectric material and having sidewalls comprising a plurality of curved protrusions, wherein the layer of dielectric material is configured as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.   
     
     
         2 . The integrated chip of  claim 1 , wherein a bottom surface of the trench comprises a curved profile extending between the serrated sidewalls. 
     
     
         3 . The integrated chip of  claim 2 , wherein the bottom surface comprises one or more curved depressions. 
     
     
         4 . The integrated chip of  claim 1 , wherein depths of the plurality of curved depressions into the substrate decrease as a distance from an upper surface of the substrate increases. 
     
     
         5 . The integrated chip of  claim 1 ,
 wherein the trench comprises an opening arranged along an upper surface of the substrate and an underlying cavity in communication with the opening; and   wherein the opening has a smaller width than the underlying cavity.   
     
     
         6 . The integrated chip of  claim 5 , wherein the underlying cavity has a width that increases as a distance from the upper surface of the substrate decreases. 
     
     
         7 . The integrated chip of  claim 1 , wherein the serrated sidewalls are oriented at a non-zero angle with respect to a normal line perpendicular to an upper surface of the substrate. 
     
     
         8 . The integrated chip of  claim 1 , wherein a sidewall angle of the serrated sidewalls changes as a function of a depth of the trench. 
     
     
         9 . The integrated chip of  claim 1 , wherein the plurality of curved depressions have depths that are non-uniform along a depth of the trench. 
     
     
         10 . The integrated chip of  claim 9 , wherein as the depths of the curved depressions into the substrate decrease as a distance from an upper surface of the substrate increases. 
     
     
         11 . The integrated chip of  claim 10 , wherein slopes of the serrated sidewalls increase as the depths of the curved depressions decrease. 
     
     
         12 . The integrated chip of  claim 1 , further comprising:
 a conductive doped region arranged within the substrate and surrounding the trench, wherein the second electrode comprises the conductive doped region.   
     
     
         13 . The integrated chip of  claim 1 , further comprising:
 a second layer of dielectric material conformally lining the layer of conductive material; and   a second layer of conductive material conformally lining the second layer of dielectric material, wherein the second electrode comprises the second layer of conductive material.   
     
     
         14 . The integrated chip of  claim 1 , further comprising:
 a first conductive contact arranged within an inter-level dielectric (ILD) layer and electrically coupled to the first electrode; and   a second conductive contact arranged within the inter-level dielectric (ILD) layer and electrically coupled to second electrode.   
     
     
         15 . An integrated chip, comprising:
 a substrate having a trench comprising serrated interior surfaces, which extends from an upper surface of the substrate to an underlying position within the substrate, wherein the trench defines an opening along the upper surface of the substrate and an underlying cavity having a larger width than the opening;   a conductive doped region surrounding the trench;   a layer of dielectric material conformally lining the serrated interior surfaces; and   a layer of conductive material arranged within the trench and separated from the substrate by the layer of dielectric material.   
     
     
         16 . The integrated chip of  claim 15 , wherein a bottom surface of the trench comprises a curved surface extending between serrated sidewalls of the trench, and having one or more curved depressions. 
     
     
         17 . The integrated chip of  claim 16 ,
 wherein the trench comprises a first serrated sidewall and a second serrated side; and   wherein sidewall angles of the first serrated sidewall and the second serrated sidewall change as a function of a depth of the trench.   
     
     
         18 . The integrated chip of  claim 15 , wherein the trench curves inward along a top of the trench so that the substrate overhangs the trench along opposing sides. 
     
     
         19 . A method of forming a deep trench capacitor, comprising:
 selectively etching a substrate to form a trench having serrated interior surfaces defining a plurality of curved depressions;   forming a layer of dielectric material within the trench, wherein the layer of dielectric material conformally lines the serrated interior surfaces; and   forming a layer of conductive material within the trench and separated from the substrate by the layer of dielectric material, wherein the layer of dielectric material is configured to act as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.   
     
     
         20 . The method of  claim 19 , wherein the serrated interior surfaces comprise sidewalls having a first plurality of curved depressions and a bottom surface connecting the sidewalls and having a second plurality of curved depressions.