Mfence and lfence micro-architectural implementation method and system

Abstract

A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

What is claimed is: 
     
         1 . A process comprising: receiving a first instruction that separates memory load instructions into older loads, the older loads being older than the first instruction, and newer loads, the newer loads being newer than the first instruction; allocating a load buffer in a memory ordering unit to the first instruction; stalling dispatches of newer loads from a memory subsystem; retiring the older loads from the memory subsystem; and dispatching the first instruction from the load buffer to a cache controller after all older loads from the memory subsystem are retired. 
     
     
         2 . The process of  claim 1  wherein the cache controller is the closest cache controller to a processor. 
     
     
         3 . The process of  claim 2  further comprising: retiring the load fencing instruction from the cache controller. 
     
     
         4 . The process of  claim 3  wherein the retirement of the older loads from the memory subsystem is via the cache controller. 
     
     
         5 . The process of  claim 3  wherein the retirement of the older loads from the memory subsystem is via the memory ordering unit. 
     
     
         6 . The process of  claim 5  wherein the retirement of the older loads from the memory subsystem is indicated by a reorder buffer retirement pointer and a load buffer tail pointer pointing to the load buffer. 
     
     
         7 . An apparatus comprising: a memory unit; a cache controller; and a memory ordering unit comprising: at least one load buffer, the memory ordering unit being operative to receive a first instruction to separate memory load instructions that access the computer readable memory into older memory loads and newer memory loads, to allocate the load buffer to the first instruction, to stall dispatches of the newer memory loads, and to dispatch the first instruction from the load buffer to a cache controller after the older memory loads are retired, wherein the older memory loads are older than the first instruction, and the newer memory loads are newer than the first instruction. 
     
     
         8 . The apparatus of  claim 7  wherein the cache controller is the closest cache controller to a processor. 
     
     
         9 . The apparatus of  claim 8 , the cache controller being operative to retire the first instruction. 
     
     
         10 . The apparatus of  claim 9 , the cache controller being further operative to retire the older memory loads. 
     
     
         11 . The apparatus of  claim 9 , the memory ordering unit being operative to retire the older memory loads. 
     
     
         12 . The apparatus of  claim 11  wherein the retirement of the older memory loads is indicated by a reorder buffer retirement pointer and a load buffer tail pointer pointing to the load buffer. 
     
     
         13 . Computer executable program code, stored on a computer readable medium, for operating a computer system by functionally configuring it to have a computer readable memory, a cache controller, a memory ordering unit with at least one load buffer, comprising program code means for: receiving a first instruction to separate memory load instructions into older loads, the older loads being older than the first instruction, and newer loads, the newer loads being newer than the first instruction; allocating a load buffer in a memory ordering unit to the first instruction; stalling dispatches of newer loads from a memory subsystem; retiring the older loads from the memory subsystem; dispatching the first instruction from the load buffer to a cache controller after the older loads from the memory subsystem are retired; and retiring the first instruction.