Inventor · disambiguated record
Stephen A. Fischer
Also filed as: FISCHER STEPHEN · FISCHER STEPHEN A · FISCHER STEPHEN ANTHONY
56 granted patents·5 pending applications·1,465 citations·filing 1990–2017
99Inventor score
Files withINTEL CORP43PALANCA SALVADOR5FISCHER STEPHEN ANTHONY3JAHAGIRDAR SANJEEV3FISCHER STEPHEN A2
Top patents by PatentIndex Score
61 records- 0195US7664970B2Method and apparatus for a zero voltage processor sleep stateINTEL CORP·Filed 2005·Granted Feb 16, 2010·38 cites·10 claims
- 0293US9223979B2Detection of return oriented programming attacksINTEL CORP·Filed 2012·Granted Dec 29, 2015·16 cites·24 claims
- 0392US6651151B2MFENCE and LFENCE micro-architectural implementation method and systemINTEL CORP·Filed 2002·Granted Nov 18, 2003·42 cites·18 claims
- 0491US6470370B2Method and apparatus for multiplying and accumulating complex numbers in a digital filterINTEL CORP·Filed 2001·Granted Oct 22, 2002·62 cites·29 claims
- 0587US8959314B2MFENCE and LFENCE micro-architectural implementation method and systemPALANCA SALVADOR·Filed 2013·Granted Feb 17, 2015·6 cites·14 claims
- 0686US8489660B2Digital random number generator using partially entropic dataHERBERT HOWARD C·Filed 2009·Granted Jul 16, 2013·24 cites·17 claims
- 0786US5936872AMethod and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operationsINTEL CORP·Filed 1995·Granted Aug 10, 1999·128 cites·40 claims
- 0886US5793661AMethod and apparatus for performing multiply and accumulate operations on packed dataINTEL CORP·Filed 1995·Granted Aug 11, 1998·131 cites·21 claims
- 0984US6823353B2Method and apparatus for multiplying and accumulating complex numbers in a digital filterINTEL CORP·Filed 2002·Granted Nov 23, 2004·31 cites·8 claims
- 1083US9342310B2MFENCE and LFENCE micro-architectural implementation method and systemINTEL CORP·Filed 2013·Granted May 17, 2016·5 cites·19 claims
- 1183US9177147B2Protection against return oriented programming attacksINTEL CORP·Filed 2012·Granted Nov 3, 2015·5 cites·24 claims
- 1283US8707062B2Method and apparatus for powered off processor core modeJAHAGIRDAR SANJEEV·Filed 2010·Granted Apr 22, 2014·4 cites·20 claims
- 1382US9251348B2Detection of return oriented programming attacksINTEL CORP·Filed 2013·Granted Feb 2, 2016·4 cites·21 claims
- 1482US5732207AMicroprocessor having single poly-silicon EPROM memory for programmably controlling optional featuresINTEL CORP·Filed 1995·Granted Mar 24, 1998·54 cites·11 claims
- 1581US9946875B2Detection of return oriented programming attacksINTEL CORP·Filed 2017·Granted Apr 17, 2018·2 cites·19 claims
- 1681US9612835B2MFENCE and LFENCE micro-architectural implementation method and systemPALANCA SALVADOR·Filed 2012·Granted Apr 4, 2017·3 cites·24 claims
- 1781US9582663B2Detection of return oriented programming attacksINTEL CORP·Filed 2015·Granted Feb 28, 2017·2 cites·20 claims
- 1881US9383998B2MFENCE and LFENCE micro-architectural implementation method and systemPALANCA SALVADOR·Filed 2012·Granted Jul 5, 2016·3 cites·24 claims
- 1981US9098268B2MFENCE and LFENCE micro-architectural implementation method and systemPALANCA SALVADOR·Filed 2012·Granted Aug 4, 2015·3 cites·24 claims
- 2081US8230203B2Detecting spin loops in a virtual machine environmentNEIGER GILBERT·Filed 2007·Granted Jul 24, 2012·11 cites·10 claims
- 2181US7370189B2Method and apparatus for establishing safe processor operating points in connection with a secure bootINTEL CORP·Filed 2004·Granted May 6, 2008·20 cites·20 claims
- 2281US6058408AMethod and apparatus for multiplying and accumulating complex numbers in a digital filterINTEL CORP·Filed 1995·Granted May 2, 2000·97 cites·14 claims
- 2380US10049212B2Protection against return oriented programming attacksINTEL CORP·Filed 2015·Granted Aug 14, 2018·2 cites·20 claims
- 2480US5467295ABus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unitINTEL CORP·Filed 1992·Granted Nov 14, 1995·73 cites·23 claims
- 2578US9544139B2Method and apparatus for a non-deterministic random bit generator (NRBG)COX GEORGE W·Filed 2011·Granted Jan 10, 2017·7 cites·8 claims
- 2678US6237016B1Method and apparatus for multiplying and accumulating data samples and complex coefficientsINTEL CORP·Filed 1997·Granted May 22, 2001·85 cites·18 claims
- 2778US5983257ASystem for signal processing using multiply-add operationsINTEL CORP·Filed 1995·Granted Nov 9, 1999·86 cites·24 claims
- 2877US9841807B2Method and apparatus for a zero voltage processor sleep stateINTEL CORP·Filed 2015·Granted Dec 12, 2017·1 cites·24 claims
- 2976US9141180B2Method and apparatus for a zero voltage processor sleep stateINTEL CORP·Filed 2015·Granted Sep 22, 2015·1 cites·6 claims
- 3076US5239639AEfficient memory controller with an independent clockINTEL CORP·Filed 1990·Granted Aug 24, 1993·75 cites·24 claims
- 3175US6185671B1Checking data type of operands specified by an instruction using attributes in a tagged array architectureINTEL CORP·Filed 1998·Granted Feb 6, 2001·82 cites·30 claims
- 3274US9727345B2Method for booting a heterogeneous system and presenting a symmetric core viewINTEL CORP·Filed 2013·Granted Aug 8, 2017·3 cites·17 claims
- 3370US6546462B1CLFLUSH micro-architectural implementation method and systemINTEL CORP·Filed 1999·Granted Apr 8, 2003·54 cites·53 claims
- 3470US5983253AComputer system for performing complex digital filtersINTEL CORP·Filed 1995·Granted Nov 9, 1999·59 cites·45 claims
- 3568US5941964ABridge buffer management by bridge interception of synchronization eventsINTEL CORP·Filed 1995·Granted Aug 24, 1999·57 cites·17 claims
- 3668US5887194ALocking protocol for peripheral component interconnect utilizing master device maintaining assertion of lock signal after relinquishing control of bus such that slave device remains lockedINTEL CORP·Filed 1995·Granted Mar 23, 1999·44 cites·9 claims
- 3768US5835392AMethod for performing complex fast fourier transforms (FFT's)INTEL CORP·Filed 1995·Granted Nov 10, 1998·52 cites·16 claims
- 3866US9177148B2Protection against return oriented programming attacksINTEL CORP·Filed 2013·Granted Nov 3, 2015·1 cites·16 claims
- 3966US8892861B2Method and apparatus for establishing safe processor operating pointsFISCHER STEPHEN ANTHONY·Filed 2012·Granted Nov 18, 2014·1 cites·21 claims
- 4066US8131989B2Method and apparatus for establishing safe processor operating pointsFISCHER STEPHEN ANTHONY·Filed 2008·Granted Mar 6, 2012·2 cites·28 claims
- 4164US9870044B2Method and apparatus for a zero voltage processor sleep stateINTEL CORP·Filed 2016·Granted Jan 16, 2018·0 cites·21 claims
- 4263US9874925B2Method and apparatus for a zero voltage processor sleep stateINTEL CORP·Filed 2015·Granted Jan 23, 2018·0 cites·5 claims
- 4363US9223389B2Method and apparatus for a zero voltage processorINTEL CORP·Filed 2014·Granted Dec 29, 2015·0 cites·19 claims
- 4463US9223390B2Method and apparatus for a zero voltage processorINTEL CORP·Filed 2014·Granted Dec 29, 2015·0 cites·19 claims
- 4562US9235258B2Method and apparatus for a zero voltage processorINTEL CORP·Filed 2014·Granted Jan 12, 2016·0 cites·18 claims
- 4662US2017206088A1Mfence and lfence micro-architectural implementation method and systemLNTEL CORP·Filed 2017·Application pending·0 cites
- 4761US8171261B2Method and system for accessing memory in parallel computing using load fencing instructionsPALANCA SALVADOR·Filed 2003·Granted May 1, 2012·4 cites·37 claims
- 4857US2013013945A1Method and apparatus for a zero voltage processor sleep stateJAHAGIRDAR SANJEEV·Filed 2012·Application pending·0 cites
- 4956US10503517B2Method for booting a heterogeneous system and presenting a symmetric core viewINTEL CORP·Filed 2017·Granted Dec 10, 2019·0 cites·15 claims
- 5056US7934076B2System and method for limiting exposure of hardware failure information for a secured execution environmentINTEL CORP·Filed 2004·Granted Apr 26, 2011·4 cites·34 claims
Showing the top 50 of 61 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →