Method and apparatus for a zero voltage processor sleep state

Abstract

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

1 . A processor, comprising:
 a voltage regulator interface to specify an operational voltage to a voltage regulator that provides said operational voltage to said processor;   zero voltage entry/exit circuitry to transition said processor to a zero voltage power management state, wherein said operational voltage is reduced to approximately zero volts, said zero voltage entry/exit circuitry to transition said processor from said zero voltage power management state, wherein said operational voltage is higher than the approximately zero volts;   a memory interface to write state variables of the processor to a memory as part of transitioning said processor to said zero voltage power management state, and to read said state variables from said memory as part of transitioning said processor from said zero voltage power management state.