Hardware profiling mechanism to enable page level automatic binary translation

Abstract

A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

What is claimed is: 
     
         1 . An apparatus comprising:
 one or more processor cores, each of the processor cores including performance monitoring hardware; and   cache units coupled to the one or more cores,   
       wherein the performance monitoring hardware includes logic to:
 identify a code page in memory containing potentially optimizable instructions; 
 request allocation of a new page in the memory associated with the code page, wherein the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page; 
 detect a branch instruction having a branch target within the code page; 
 increment one of the counters that has the same position in the new page as the branch target in the code page; 
 repeat execution of the code page and incrementing the counters when branch targets fall within the code page; and 
 provide values of the counters in the new page to a binary translator for binary translation. 
 
     
     
         2 . The apparatus of  claim 1 , wherein the new page is used by the binary translator to hold code translated from the code page, thereby replacing the values of the counters. 
     
     
         3 . The apparatus of  claim 2 , wherein the code translated from the code page is sharable among different threads. 
     
     
         4 . The apparatus of  claim 1 , wherein the performance monitoring hardware is further adapted to:
 after identifying the code page, pass a physical address identifying the code page to the binary translator to thereby allow the binary translator to determine whether the code page has been translated before; and   in response to a determination that the code page has been translated before, obtain a physical address of a translated code page and executing the translated code page without requesting the new page to be allocated.   
     
     
         5 . The apparatus of  claim 1 , wherein the size of each counter is not larger than the granularity of instructions in the code page. 
     
     
         6 . The apparatus of  claim 1 , wherein each of the counters saturates at a maximum value and does not roll over back to zero. 
     
     
         7 . The apparatus of  claim 1 , wherein the code page is translated into position independent code. 
     
     
         8 . A method comprising:
 identifying, by performance monitoring hardware during runtime, a code page in memory containing potentially optimizable instructions;   requesting allocation of a new page in the memory associated with the code page, wherein the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page;   detecting a branch instruction having a branch target within the code page;   incrementing one of the counters that has the same position in the new page as the branch target in the code page;   repeating execution of the code page and incrementing the counters when branch targets fall within the code page; and   providing values of the counters in the new page to a binary translator for binary translation.   
     
     
         9 . The method of  claim 8 , wherein the new page is used by the binary translator to hold code translated from the code page, thereby replacing the values of the counters. 
     
     
         10 . The method of  claim 9 , wherein the code translated from the code page is sharable among different threads. 
     
     
         11 . The method of  claim 8 , further comprising:
 after identifying the code page, passing a physical address identifying the code page to the binary translator to thereby allow the binary translator to determine whether the code page has been translated before; and   in response to a determination that the code page has been translated before, obtaining a physical address of a translated code page and executing the translated code page without requesting the new page to be allocated.   
     
     
         12 . The method of  claim 8 , wherein the size of each counter is not larger than the granularity of instructions in the code page. 
     
     
         13 . The method of  claim 8 , wherein each of the counters saturates at a maximum value and does not roll over back to zero. 
     
     
         14 . The method of  claim 8 , wherein the code page is translated into position independent code. 
     
     
         15 . A system comprising:
 memory to store a plurality of code pages;   a processor coupled to the memory, the processor including performance monitoring hardware, which includes logic to:
 identify, during runtime, one of the code pages containing potentially optimizable instructions; 
 request allocation of a new page in the memory associated with the identified code page, wherein the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the identified code page; 
 detect a branch instruction having a branch target within the identified code page; 
 increment one of the counters that has the same position in the new page as the branch target in the identified code page; 
 repeat execution of the identified code page and incrementing the counters when branch targets fall within the identified code page; and 
 provide values of the counters in the new page to a binary translator for binary translation. 
   
     
     
         16 . The system of  claim 15 , wherein the new page is used by the binary translator to hold code translated from the code page, thereby replacing the values of the counters. 
     
     
         17 . The system of  claim 16 , wherein the code translated from the code page is sharable among different threads. 
     
     
         18 . The system of  claim 15 , wherein the performance monitoring hardware is further adapted to:
 after identifying the code page, pass a physical address identifying the code page to the binary translator to thereby allow the binary translator to determine whether the code page has been translated before; and   in response to a determination that the code page has been translated before, obtain a physical address of a translated code page and executing the translated code page without requesting the new page to be allocated.   
     
     
         19 . The system of  claim 15 , wherein each of the counters saturates at a maximum value and does not roll over back to zero. 
     
     
         20 . The system of  claim 15 , wherein the code page is translated into position independent code.