Memory Controller For Heterogeneous Configurable Integrated Circuit

Abstract

A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

What is claimed is: 
     
         1 . A method for routing data in a configurable integrated circuit, comprising:
 programming a plurality of interconnect stations into a station mesh for high speed data transfer;   configuring a plurality of programmable logic blocks (“PLBs”) into a PLB array mesh for performing logic functions;   programming a plurality of pipelined buses between the station mesh to facilitate high speed data transfer between the interconnect stations; and   selectively linking at least a portion of the plurality of interconnect stations to a portion of the plurality of PLB s to merge the station mesh into the PLB array mesh to form a high speed communications fabric.   
     
     
         2 . The method of  claim 1 , further comprising programming a portion of the plurality of PLBs to perform a function of memory control. 
     
     
         3 . The method of  claim 1 , further comprising configuring a special purpose block into the high speed communications fabric. 
     
     
         4 . The method of  claim 1 , wherein programming a plurality of interconnect stations into a station mesh includes arranging interconnect stations in an array configuration. 
     
     
         5 . The method of  claim 4 , wherein arranging interconnect stations includes allowing each interconnect station having at least two neighboring interconnect stations. 
     
     
         6 . The method of  claim 1 , wherein configuring a plurality of PLBs into a PLB array mesh includes arranging PLBs in a logical array configuration separated by at least one interconnect station. 
     
     
         7 . The method of  claim 6 , wherein arranging PLBs in a logical array configuration includes allowing each PLB having at least one connection to a neighboring interconnect station. 
     
     
         8 . The method of  claim 1 , wherein programming a plurality of pipelined buses between the station mesh includes configuring connectivity of a least portion of the pipelined buses in accordance with values stored in a configuration register. 
     
     
         9 . The method of  claim 1 , wherein selectively linking at least a portion of the plurality of interconnect stations to a portion of the plurality of PLBs includes configuring connectivity between at least a portion of the interconnect stations and a portion of PLBs in accordance with values stored in a configuration register. 
     
     
         10 . The method of  claim 1 , wherein programming a plurality of pipelined buses between the station mesh includes coupling an output ramp of a first interconnect station to an input ramp of a second interconnect station via a pipelined bus. 
     
     
         11 . The method of  claim 1 , wherein selectively linking at least a portion of the plurality of interconnect stations to a portion of the plurality of PLBs includes coupling an output port of a first interconnect station to an input port of a PLB for facilitating performance of a logic function. 
     
     
         12 . A configurable integrated circuit, comprising:
 a plurality of interconnect stations configured to programmably couple to a station mesh for high speed data transfer;   a plurality of programmable logic blocks (“PLBs”) coupled to the plurality of interconnect stations and configured into a PLB array mesh for performing logic functions;   a plurality of pipelined buses between the station mesh capable of being programmed to facilitate high speed data transfer between the interconnect stations; and   a portion of the plurality of interconnect stations coupled to the plurality of interconnect station and configured to selectively link to a portion of the plurality of PLBs to merge the station mesh into the PLB array mesh to form a high speed communications fabric.   
     
     
         13 . The circuit of  claim 12 , wherein a portion of the plurality of PLBs is programmed to perform a function of memory control. 
     
     
         14 . The circuit of  claim 12 , further comprising a special purpose block configured to facilitate managing the high speed communications fabric. 
     
     
         15 . The circuit of  claim 12 , wherein the plurality of interconnect stations into a station mesh is arranged in an array configuration. 
     
     
         16 . The circuit of  claim 13 , wherein arranging interconnect stations includes allowing each interconnect station having at least two neighboring interconnect stations. 
     
     
         17 . The circuit of  claim 12 , wherein at least a portion of the plurality of PLBs is separated by at least one interconnect station. 
     
     
         18 . The method of  claim 17 , wherein each of the plurality of PLBs has at least one connection to a neighboring interconnect station. 
     
     
         19 . A method for routing data in a configurable integrated circuit, comprising:
 programming a plurality of interconnect stations into a station mesh for high speed data transfer;   configuring a plurality of programmable logic blocks (“PLBs”) into a PLB array mesh for performing logic functions;   programming a plurality of pipelined buses between the station mesh to facilitate high speed data transfer between the interconnect stations;   selectively linking at least a portion of the plurality of interconnect stations to a portion of the plurality of PLB s to merge the station mesh into the PLB array mesh to form a high speed communications fabric; and   setting values in a configuration register via a dedicated interface.   
     
     
         20 . The method of  claim 1 , further comprising:
 programming a portion of the plurality of PLBs to perform a function of memory control; and   configuring a special purpose block into the high speed communications fabric.