Capped electrode contact for rram cells and memory cell arrays

Abstract

Exemplary embodiments of the present invention are directed towards a method for fabricated a memory cell comprising depositing a material to form an interface cap above a bulk conductive plug and below active cell materials in the memory cell.

What is claimed is: 
     
         1 . A memory cell comprising:
 a dielectric layer;   a substrate disposed at a first side of the dielectric layer;   one or more layers of an active cell material disposed at a second side of the dielectric layer; and   a via disposed within the dielectric layer between the substrate and the one or more layers of the active cell material, wherein the via includes a conductive material disposed within the via at a first end of the via closest to the substrate and a first material disposed within the via at a second end of the via closest to the one or more layers of the active cell material.   
     
     
         2 . The memory cell of  claim 1 , wherein the memory cell is one of a phase-change memory, a resistive ram (ReRAM), a conductive-bridge RAM (CBRAM), or a logic gate. 
     
     
         3 . The memory cell of  claim 1 , wherein the first material is Tungsten (W) and the conductive material is TDMAT TiN. 
     
     
         4 . The memory cell of  claim 1 , wherein the first material is Tungsten (W) and the conductive material is CVD TiN. 
     
     
         5 . The memory cell of  claim 1 , wherein the first material is disposed on a portion of the conductive material within the via. 
     
     
         6 . The memory cell of  claim 1 , wherein the first material interfacial has a width greater than or equal to a height within the via. 
     
     
         7 . The memory cell of  claim 1 , wherein the first material includes a grain structure different from a grain structure of the conductive material in the via. 
     
     
         8 . The memory cell of  claim 1 , wherein the first material includes carbon. 
     
     
         9 . The memory cell of  claim 1 , wherein the first material has a higher energy of formation than the conductive material in the via. 
     
     
         10 . The memory cell of  claim 1 , wherein the first material includes one of TDMAT TiN (TiCN), Tantalum Nitrogen (TaN), WCN or TiAIN. 
     
     
         11 . An electronic device comprising a plurality of memory tiles including an array of memory cells, each cell including:
 a dielectric layer;   a substrate disposed at a first side of the dielectric layer;   one or more layers of an active cell material disposed at a second side of the dielectric layer; and   a via disposed within the dielectric layer between the substrate and the one or more layers of the active cell material, wherein the via includes a conductive material disposed within the via at a first end of the via closest to the substrate and a first material disposed within the via at a second end of the via closest to the one or more layers of the active cell material.   
     
     
         12 . The electronic device of  claim 11 , wherein the memory cell is one of a phase-change memory, a resistive ram (ReRAM), a conductive-bridge RAM (CBRAM), or a logic gate. 
     
     
         13 . The electronic device of  claim 11 , wherein the first material is Tungsten (W) and the conductive material is TDMAT TiN. 
     
     
         14 . The electronic device of  claim 11 , wherein the first material is Tungsten (W) and the conductive material is CVD TiN. 
     
     
         15 . The electronic device of  claim 11 , wherein the first material is disposed on a portion of the conductive material within the via. 
     
     
         16 . The electronic device of  claim 11 , wherein the first material interfacial has a width greater than or equal to a height within the via. 
     
     
         17 . The electronic device of  claim 11 , wherein the first material includes a grain structure different from a grain structure of the conductive material in the via. 
     
     
         18 . The electronic device of  claim 11 , wherein the first material includes carbon. 
     
     
         19 . The electronic device of  claim 11 , wherein the first material has a higher energy of formation than the conductive material in the via. 
     
     
         20 . The electronic device of  claim 11 , wherein the first material includes one of TDMAT TiN (TiCN), Tantalum Nitrogen (TaN), WCN or TiAIN.