Thin film transistor substrate, a display device including the same, and a method of manufacturing the same

Abstract

A thin film transistor substrate including a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer including a channel region, and a source region and a drain region at first and second sides of the channel region; a gate electrode disposed on the semiconductor layer; a gate insulating layer disposed between the gate electrode and the semiconductor layer; and a first insulating layer disposed on the substrate, the first insulating layer exposes the upper surface of the gate electrode and surrounds the gate electrode.

What is claimed is: 
     
         1 . A thin film transistor substrate, comprising:
 a substrate;   a semiconductor layer disposed on the substrate, the semiconductor layer comprising a channel region, and a source region and a drain region at first and second sides of the channel region;   a gate electrode disposed on the semiconductor layer;   a gate insulating layer disposed between the gate electrode and the semiconductor layer; and   a first insulating layer disposed on the substrate, wherein the first insulating layer exposes an upper surface of the gate electrode and surrounds the gate electrode.   
     
     
         2 . The thin film transistor substrate of  claim 1 , further comprising:
 a first hole in the first insulating layer, wherein the gate electrode is disposed within the first hole.   
     
     
         3 . The thin film transistor substrate of  claim 1 , wherein the upper surface of the gate electrode and an upper surface of the first insulating layer meet at the same plane. 
     
     
         4 . The thin film transistor substrate of  claim 1 , further comprising:
 a second insulating layer disposed on the upper surface of the gate electrode and an upper surface of the first insulating layer.   
     
     
         5 . The thin film transistor substrate of  claim 4 , further comprising:
 an auxiliary electrode disposed on the second insulating layer, wherein the auxiliary electrode contacts the gate electrode via a contact hole in the second insulating layer.   
     
     
         6 . The thin film transistor substrate of  claim 5 , further comprising:
 an electrode disposed on the second insulating layer,   wherein the electrode is electrically connected to at least one of the source region and the drain region.   
     
     
         7 . The thin film transistor substrate of  claim 6 , wherein the electrode comprises:
 a first electrode layer contacting at least one of the source region and the drain region; and   a second electrode layer disposed on the first electrode layer, wherein the second electrode layer contacts the first electrode layer.   
     
     
         8 . The thin film transistor substrate of  claim 7 , wherein the first electrode layer comprises a same material as the gate electrode. 
     
     
         9 . The thin film transistor substrate of  claim 7 , further comprising:
 a second hole disposed in the first insulating layer and exposing at least one of the source region and the drain region, wherein the first electrode layer is disposed within the second hole.   
     
     
         10 . The thin film transistor substrate of  claim 7 , wherein the first insulating layer surrounds the first electrode layer and exposes an upper surface of the first electrode layer. 
     
     
         11 . The thin film transistor substrate of  claim 7 , wherein the second electrode layer is disposed on the second insulating layer, the second electrode layer contacting the first electrode layer via a hole in the second insulating layer. 
     
     
         12 . The thin film transistor substrate of  claim 1 , wherein the upper surface of the gate electrode has a width greater than a width of a lower surface of the gate electrode. 
     
     
         13 . The thin film transistor substrate of  claim 1 , wherein a length of the semiconductor layer in a first direction is greater than a length of the gate insulating layer in the first direction. 
     
     
         14 . A display device, comprising:
 the thin film transistor substrate of  claim 1 ; and   a display element disposed on the thin film transistor substrate.   
     
     
         15 . The display device of  claim 14 , wherein the display element comprises an organic light-emitting diode. 
     
     
         16 . The display device of  claim 14 , wherein the display element comprises a liquid crystal capacitor. 
     
     
         17 . A method of manufacturing a thin film transistor substrate, the method comprising:
 forming a semiconductor layer on a substrate, the semiconductor layer comprising a channel region, and a source region and a drain region at first and second sides of the channel region;   forming a gate insulating layer on the semiconductor layer;   forming a first preliminary insulating layer on the gate insulating layer;   forming a first hole in the first preliminary insulating layer;   forming a metallic layer on the first preliminary insulating layer, the metallic layer comprising a first portion filling the first hole; and   removing the first preliminary insulating layer and the metallic layer, wherein a portion of the first preliminary insulating layer and at least a portion of the first portion of the metallic layer remain, and wherein   the remaining portion of the first preliminary insulating layer is a first insulating layer covering the semiconductor layer and the gate insulating layer, and the remaining portion of the first portion of the metallic layer is a gate electrode.   
     
     
         18 . The method of  claim 17 , wherein the first insulating layer surrounds the gate electrode and exposes an upper surface of the gate electrode. 
     
     
         19 . The method of  claim 17 , wherein the gate insulating layer is exposed via the first hole. 
     
     
         20 . The method of  claim 17 , wherein the removing of the first preliminary insulating layer and the metallic layer is performed using chemical mechanical polishing (CMP). 
     
     
         21 . The method of  claim 17 , wherein an upper surface of the gate electrode and an upper surface of the first insulating layer meet at the same plane. 
     
     
         22 . The method of  claim 17 , wherein the forming of the first hole is performed using dry etching. 
     
     
         23 . The method of  claim 17 , further comprising:
 forming a second insulating layer, the second insulating layer covering the gate electrode and the first insulating layer.   
     
     
         24 . The method of  claim 23 , further comprising:
 forming an auxiliary electrode on the second insulating layer, the auxiliary electrode contacting the gate electrode via a hole in the second insulating layer.   
     
     
         25 . The method of  claim 23 , further comprising:
 forming a second hole in the first preliminary insulating layer, the forming of the second hole and the forming of the first hole being performed by a same process.   
     
     
         26 . The method of  claim 25 , wherein
 the second hole exposes at least one of the source region and the drain region;   a second portion of the metallic layer fills the second hole; and   the removing of the first preliminary insulating layer and the metallic layer leaves at least a portion of the second portion of the metallic layer.   
     
     
         27 . The method of  claim 26 , wherein the first insulating layer surrounds at least a portion of the first portion of the metallic layer, and
 wherein the first insulating layer exposes an upper surface of at least a portion of the first portion of the metallic layer.   
     
     
         28 . The method of  claim 26 , further comprising:
 forming an electrode layer on the second insulating layer, the electrode layer contacting at least a portion of the second portion of the metallic layer via a hole in the second insulating layer.   
     
     
         29 . The method of  claim 17 , wherein the forming of the semiconductor layer and the forming of the gate insulating layer are performed by a same mask process. 
     
     
         30 . The method of  claim 17 , further comprising:
 performing wet washing on the first preliminary insulating layer, wherein the first hole is disposed in the first preliminary insulating layer.