Phase-change memory cell having a compact structure

Abstract

A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

1 . A process for fabricating a memory cell, the process comprising:
 covering a semiconductor substrate with a first insulating layer;   covering the first insulating layer with an active layer made of a semiconductor material;   forming a first control gate and first and second conduction terminals of a first selection transistor;   covering, with a second insulating layer, a lateral flank of the first control gate on the same side as the first conduction terminal;   producing a first trench through the active layer in the first conduction terminal, reaching the first insulating layer;   depositing a first layer in the first trench, covering a lateral flank of the active layer in the trench; and   depositing a second layer in contact with the first layer, wherein one of the first and second layers is made of a variable-resistance material.   
     
     
         2 . The process according to  claim 1 , in which the first layer is made of the variable-resistance material. 
     
     
         3 . The process according to  claim 2 , comprising depositing, on a lateral flank of the first layer, a third insulating layer, and etching a second trench in the first layer along the third insulating layer, until the first insulating layer is reached. 
     
     
         4 . The process according to  claim 3 , comprising filling the second trench with a conductor in order to form a trench conductor. 
     
     
         5 . The process according to  claim 3 , comprising filling the second trench with an insulator and depositing on the second trench a conductor making contact with the first layer. 
     
     
         6 . The process according to  claim 1 , in which the second layer is made of the variable-resistance material, extends longitudinally in a plane parallel to the surface of the substrate and makes contact with an upper portion of the first layer, the first layer being a resistor configured to heat the second layer in order to make the second layer change phase between a non-conductive amorphous phase and a conductive crystalline phase. 
     
     
         7 . The process according to  claim 1 , further comprising:
 forming a second control gate and a third conduction terminal, a second selection transistor including the first conduction terminal, the second control gate and the third conduction terminal; and   covering, with the second insulating layer, a lateral flank of the second control gate.   
     
     
         8 . The process according to  claim 7 , in which depositing a first layer in the first trench includes covering a second lateral flank of the active layer in the trench. 
     
     
         9 . The process according to  claim 7 , wherein the first layer is a heater, and the second layer is the variable-resistance material. 
     
     
         10 . A method, comprising:
 forming an active layer having a source region and a drain region;   forming a first gate on a first portion of the active layer between the source region and the drain region; and   forming a variable-resistance element coupled to one of the source and drain regions, the forming the variable resistance element including:
 forming a first layer in a first trench, the first trench being in the one of the source and drain regions; and 
 forming a second layer in contact with the first layer, wherein one of the first and second layers is made of a variable-resistance material. 
   
     
     
         11 . The method of  claim 10  wherein forming the variable-resistance element includes forming the first layer of the variable-resistance material. 
     
     
         12 . The method of  claim 11  wherein forming the variable-resistance element includes forming the second layer of the variable-resistance material. 
     
     
         13 . The method of  claim 12  wherein forming the variable-resistance element includes forming the first layer of a resistive heater material. 
     
     
         14 . The method of  claim 12  wherein forming the variable-resistance element includes forming the second layer in a plane parallel to a surface of the active layer. 
     
     
         15 . The method of  claim 12 , further comprising:
 forming a dielectric between a portion of the first layer and a portion of the second layer, a portion of the dielectric layer in the trench.   
     
     
         16 . The process of  claim 10 , further comprising:
 forming a second gate on a second portion of the active layer, the one of the source and drain regions being between the first portion and the second portion of the active layer; and   forming a third layer in the first trench, the third layer closer to the second portion of the active layer than the first layer, the third layer being the same material as the first layer.   
     
     
         17 . A method, comprising:
 forming a memory plane of memory cells, the forming a memory plane including:
 forming a first insulating layer on a surface of a semiconductor substrate; 
 forming an active layer of semiconductor material on the first insulating layer; and 
 forming at least one pair of memory cells, the forming the at least one pair of memory cells including:
 forming a first selection transistor having a first conduction region and a second conduction region in the active layer and a gate on a first portion of the active layer between the first and second conduction regions of the first selection transistor; 
 forming a second selection transistor having a first conduction region and a second conduction region in the active layer and a gate on a second portion of the active layer between the first and second conduction regions of the second selection transistor, the second conduction region of the first selection transistor being the same region a the second conduction region of the second selection transistor; 
 forming a trench that extends through the second conduction region from a first side of the active layer to a second side of the active layer opposite the first side; and 
 forming a variable-resistance element electrically coupled to the first conduction region of the first and second selection transistors, the forming a variable resistance element including:
 forming a first layer on a first lateral flank of the active layer in the trench and a second lateral flank of the active layer in the trench, the first lateral flank opposite the second lateral flank; and 
 forming a second layer contacting the first layer on the first lateral flank and on the second lateral flank, wherein one of the first and second layers is made of a variable-resistance material. 
 
 
   
     
     
         18 . The method of  claim 17  wherein forming the variable-resistance element includes forming the first layer of the variable-resistance material. 
     
     
         19 . The method of  claim 17  wherein forming the variable-resistance element includes forming the second layer of the variable-resistance material. 
     
     
         20 . The method of  claim 19 , wherein the forming the first layer includes forming the first layer of a resistive heater material.