Vertical memory devices

Abstract

A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.

What is claimed is: 
     
         1 . A vertical memory device, comprising:
 a lower circuit pattern on a substrate;   a plurality of gate electrodes on the lower circuit pattern, the plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate;   a channel extending through the gate electrodes in the first direction;   a memory cell block including a first common source line (CSL), the first CSL extending in a second direction substantially parallel to the upper surface of the substrate; and   a first contact plug connected to the lower circuit pattern and the first CSL, the first contact plug overlapping the first CSL in the first direction.   
     
     
         2 . The vertical memory device of  claim 1 , wherein the first CSL is formed at a central portion of the memory cell block in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction. 
     
     
         3 . The vertical memory device of  claim 2 , wherein the memory cell block further includes,
 a plurality of second contact plugs, at least one of the second contact plugs spaced apart from the first CSL in the second direction and having a length substantially the same as that of the first CSL in the first direction.   
     
     
         4 . The vertical memory device of  claim 3 , further comprising:
 a plurality of third contact plugs under the second contact plugs, respectively, at least one of the third contact plugs being connected to the lower circuit pattern.   
     
     
         5 . The vertical memory device of  claim 3 , further comprising:
 a bit line connected to the channel, the bit line extending in the third direction substantially parallel to the upper surface of the substrate and crossing the second direction; and   a dummy bit line spaced apart from the bit line, the dummy bit line extending in the third direction and not being connected to the channel,   wherein the dummy bit line is connected to at least one of the second contact plugs.   
     
     
         6 . The vertical memory device of  claim 5 , wherein the dummy bit line includes,
 a plurality of first extension portions extending in the third direction, and   a connection portion configured to connect the first extension portions to each other, the connection portion overlapping the second contact plugs in the first direction.   
     
     
         7 . The vertical memory device of  claim 3 , wherein the memory cell block includes,
 a cell array region at a central portion in the second direction, and   a pad region at opposite edge portions in the second direction,   and wherein the first CSL is formed in the cell array region, and at least one of the plurality of second contact plugs is formed in the pad region.   
     
     
         8 . The vertical memory device of  claim 7 , wherein the gate electrodes are stacked in a staircase shape in the pad region,
 and wherein the vertical memory device further comprises fourth contact plugs contacting upper surfaces of the gate electrodes, respectively.   
     
     
         9 . The vertical memory device of  claim 8 , wherein the fourth contact plugs are connected to corresponding ones of the second contact plugs, respectively. 
     
     
         10 . The vertical memory device of  claim 3 , wherein the first contact plug includes polysilicon, and the first CSL and the second contact plugs include substantially the same metal. 
     
     
         11 . The vertical memory device of  claim 1 , wherein the memory cell block includes a plurality of memory cell blocks in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction,
 and wherein the vertical memory device further comprises a plurality of second CSLs between the memory cell blocks, at least one of the second CSLs extending in the second direction.   
     
     
         12 . The vertical memory device of  claim 1 , further comprising:
 an insulating interlayer on the substrate, the insulating interlayer covering the lower circuit pattern; and   a base layer between the insulating interlayer and the memory cell block,   wherein the first contact plug extends through an upper portion of the insulating interlayer and the base layer.   
     
     
         13 . The vertical memory device of  claim 1 , further comprising a capping pattern between the lower circuit pattern and the first contact plug, the capping pattern being doped with impurities. 
     
     
         14 . A vertical memory device, comprising:
 a lower circuit pattern on a substrate;   a plurality of gate electrodes on the lower circuit pattern, the plurality of gate electrodes being spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate;   a channel extending through the gate electrodes in the first direction;   a memory cell block including a plurality of conductive patterns extending in a second direction substantially parallel to the upper surface of the substrate, at least one of the conductive patterns extending at least a portion of the gate electrodes; and   a first contact plug connected to the lower circuit pattern, the first contact plug being under the plurality of conductive patterns.   
     
     
         15 . The vertical memory device of  claim 14 , wherein the conductive patterns are in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction,
 and wherein the vertical memory device further includes,   a CSL extending in the second direction at a central portion of the memory cell block in the second direction, and   a plurality of second contact plugs at opposite edge portions of the memory cell block in the second direction.   
     
     
         16 . A semiconductor device comprising:
 a substrate;   a first active region on the substrate;   a plurality of first impurity regions in the first active region;   a first insulating layer on the first active region;   a base layer on the first insulating layer;   a plurality of second impurity regions in the base layer;   a plurality of circuits on top of the base layer;   a conductive region in the plurality of circuits; and   a contact plug connected to the conductive region and to the first active region, the contact plug under the conductive region.   
     
     
         17 . The semiconductor device of  claim 16 , wherein
 the plurality of second impurity regions includes group III or group V elements.   
     
     
         18 . The semiconductor device of  claim 16 , wherein
 the contact plug includes polysilicon.   
     
     
         19 . The semiconductor device of  claim 16 , wherein
 the base layer includes polysilicon.   
     
     
         20 . The semiconductor device of  claim 16 , wherein
 the base layer includes a metal.