Power Semiconductor Device with Charge Balance Design

Abstract

A semiconductor body having first and second vertically spaced apart surfaces is formed. A gate trench that vertically extends from the first surface of the semiconductor body towards the second surface is formed. A gate electrode and a gate dielectric are formed in the gate trench. The gate dielectric electrically insulates the gate electrode from adjacent semiconductor material. A doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body is formed. The doped superjunction region includes first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another. The second pillar is laterally centered between the first and third pillars and has an opposite conductivity type as the first and third pillars.

1 . A method of forming a vertical trenched gate transistor, comprising:
 forming a semiconductor body comprising first and second vertically spaced apart surfaces, a gate trench that vertically extends from the first surface of the semiconductor body towards the second surface, a gate electrode disposed in the gate trench, and a gate dielectric disposed in the gate trench and electrically insulating the gate electrode from adjacent semiconductor material; and   forming a doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body, the doped superjunction region comprising first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another, the second pillar laterally centered between the first and third pillars and having an opposite conductivity type as the first and third pillars.   
     
     
         2 . The method of  claim 1 , wherein forming the semiconductor body comprises:
 providing a first semiconductor layer of a first conductivity type and having first and second vertically spaced apart surfaces; and   epitaxially depositing a second semiconductor layer of the first conductivity type on the first semiconductor layer,   wherein the doped superjunction is formed by applying semiconductor processing to the first surface of the first semiconductor layer before epitaxially depositing the second semiconductor layer.   
     
     
         3 . The method of  claim 2 , wherein forming the doped superjunction region comprises:
 forming a first trench in the first semiconductor layer vertically extending from the first surface of the first semiconductor layer;   forming a first doped semiconductor region of the first conductivity type around a perimeter of the first trench such that the first doped semiconductor region lines a bottom and sidewalls of the first trench;   forming a second doped semiconductor region of a second conductivity type that is opposite form the first conductivity type in the first trench between sections of the first doped semiconductor region that line the sidewalls of the first trench; and   wherein the second doped semiconductor region provides the second doped pillar of the doped superjunction region, and   wherein the sections of the first doped semiconductor region that line the sidewalls of the first trench provide the first and third doped pillars of the doped superjunction region.   
     
     
         4 . The method of  claim 3 , wherein forming the first doped region comprises implanting dopant atoms into the perimeter of the first trench, the dopant atoms penetrating the bottom and sidewalls of the first trench thereby forming the first doped region within the first semiconductor layer. 
     
     
         5 . The method of  claim 3 , wherein forming the first doped region around the perimeter of the first trench comprises epitaxially depositing a third semiconductor layer that lines the bottom and sidewalls of the first trench thereby forming the first doped region within the first trench, wherein a thickness of the third semiconductor layer is controlled such that a void remains in the first trench between sections of the third semiconductor layer. 
     
     
         6 . The method of  claim 3 , wherein forming the second doped semiconductor region comprises, after forming the first doped region, epitaxially depositing a fourth semiconductor layer that completely fills the first trench. 
     
     
         7 . The method of  claim 2 , wherein forming the doped superjunction region comprises:
 performing masked ion implantation at the first surface of the first semiconductor layer before epitaxially depositing the second semiconductor layer thereby forming doped wells that vertically extend from the first surface of the first semiconductor layer into the first semiconductor layer.   
     
     
         8 . The method of  claim 7 , wherein performing masked ion implantation comprises forming first and second doped wells that vertically extend from the first surface of the first semiconductor layer into the first semiconductor layer, the first doped well being wider than the second doped well, the second doped well being arranged in a lateral center of the first doped well such that portions of the first well are disposed on both lateral sides of the second well, wherein the second doped well provides the second doped pillar of the doped superjunction region, and wherein the portions of the first well that are disposed on both lateral sides of the second well provide the first and third doped pillars of the doped superjunction region. 
     
     
         9 . The method of  claim 7 , wherein performing masked ion implantation comprises forming first, second, and third wells of approximately equal width that directly laterally adjoin one another, wherein the second well is laterally interposed between the first and third wells, wherein the second well provides the second doped pillar of the doped superjunction region, and wherein the first and third wells provide the first and third doped pillars of the doped superjunction region. 
     
     
         10 . The method of  claim 1 , wherein forming the semiconductor body comprises providing a first semiconductor layer of a first conductivity type and having first and second vertically spaced apart surfaces, wherein the gate trench is formed by etching semiconductor material from the first surface of the first semiconductor layer, wherein the doped superjunction region is formed by implanting first and second conductivity type dopants into a bottom of the gate trench. 
     
     
         11 . The method of  claim 1 , wherein the second doped pillar has a second conductivity type that is opposite the first conductivity type, and wherein the first and third doped pillars have the first conductivity type and are more highly doped than the first semiconductor layer. 
     
     
         12 . The method of  claim 1 , wherein the second doped pillar has the first conductivity type and is more highly doped than the first semiconductor layer, and wherein the first and third doped pillars have a second conductivity type that is opposite the first conductivity type. 
     
     
         13 . The method of  claim 1 , further comprising:
 forming a second conductivity type body region vertically extending from the first surface semiconductor body, the second conductivity type being opposite the first conductivity type;   forming a first conductivity type source region that is contained within the second conductivity type body region and directly adjoins the first surface of the semiconductor body and the gate trench;   forming a second conductivity type collector region that extends from the second surface of the semiconductor body towards the gate trench; and   forming a first conductivity type field stop region that is disposed between the collector region and the drift region,   wherein a drift region of the device comprises first conductivity type semiconductor material disposed between the body region and the field stop region, and   wherein a distance between a bottom of the doped superjunction region and the field stop region is greater than 50% of a vertical thickness of the drift region, the vertical thickness of the drift region being measured as a shortest distance between the body region and the field stop region.   
     
     
         14 . The method of  claim 13 , wherein the distance between the bottom of the doped superjunction region and the field stop region is greater than 70% of a vertical thickness of the drift region. 
     
     
         15 . The method of  claim 1 , wherein semiconductor body comprises silicon, and wherein providing the semiconductor body comprises at least one of:
 providing a bulk silicon substrate and epitaxially growing one or more semiconductor layers having the first conductivity type on the bulk silicon substrate;   providing a FZ (floating zone) silicon wafer with an intrinsic doping of the first conductivity type;   providing a MCZ (magnetic Czochralski) silicon wafer with an intrinsic doping of the first conductivity type.   
     
     
         16 . The method of  claim 1 , wherein the semiconductor body comprises silicon-carbide. 
     
     
         17 . A method of forming a vertical trenched gate transistor in a semiconductor body, the semiconductor body having first and second vertically spaced apart surfaces, the vertical trenched gate transistor comprising an n-type source region extending form the first surface into the semiconductor body, a p-type body region disposed beneath and adjoining the source region, an n-type drift region disposed beneath and adjoining the body region, an n-type field stop region that is more highly doped than the drift region disposed beneath and adjoining the doped n-type drift region, a gate trench extending from the first surface through the source and body regions, and a gate electrode disposed in the gate trench and being configured to control a vertical current flowing between the first and second surfaces, the method comprising:
 forming a doped superjunction region vertically extending from a bottom of the gate trench towards the second surface of the semiconductor body, the doped superjunction region comprising first, second, and third doped pillars vertically extending from the first surface of the first semiconductor layer and directly adjoining one another, the second pillar laterally centered between the first and third pillars and having an opposite conductivity type as the first and third pillars.   
     
     
         18 . The method of  claim 17 , wherein the semiconductor body is provided by:
 providing a first semiconductor layer of a first conductivity type and having first and second vertically spaced apart surfaces; and   epitaxially depositing a second semiconductor layer of the first conductivity type on the first semiconductor layer,   wherein the doped superjunction is formed by applying semiconductor processing to the first surface of the first semiconductor layer before epitaxially depositing the second semiconductor layer.   
     
     
         19 . The method of  claim 18 , wherein forming the doped superjunction region comprises:
 forming a first trench that vertically extends beneath the first surface of the first semiconductor layer before epitaxially depositing the second semiconductor layer;   forming a first doped semiconductor region around a perimeter of the first trench such that the first doped semiconductor region lines a bottom and sidewalls of the first trench; and   forming a second doped semiconductor region in the first trench between sections of the first doped semiconductor region that line the sidewalls of the first trench,   wherein forming the first doped semiconductor region comprises at least one of:   implanting n-type dopant atoms into the perimeter of the first trench; and   epitaxially depositing a third n-type semiconductor layer that lines the bottom and sidewalls of the first trench.   
     
     
         20 . The method of  claim 18 , wherein forming the doped superjunction region comprises:
 performing masked ion implantation at the first surface of the first semiconductor layer before epitaxially depositing the second semiconductor layer thereby forming doped wells that vertically extend beneath the first surface of the first semiconductor layer.   
     
     
         21 . The method of  claim 18 , wherein the semiconductor body is provided by a first semiconductor layer of a first conductivity type and having first and second vertically spaced apart surfaces, wherein the gate trench is formed by etching semiconductor material from the first surface of the first semiconductor layer, wherein the doped superjunction region is formed by implanting first and second conductivity type dopants into a bottom of the gate trench. 
     
     
         22 . A vertical trenched gate transistor being formed in a semiconductor body having first and second vertically spaced apart surfaces, the vertical trenched gate transistor comprising:
 an n-type source region extending form the first surface into the semiconductor body;   a p-type body region disposed beneath and adjoining the source region;   an n-type drift region disposed beneath the body region;   an n-type field stop region that is more highly doped than the drift region disposed beneath and adjoining the drift region;   a gate trench extending from the first surface through the source and body regions, and a gate electrode disposed in the gate trench and being configured to control a vertical current flowing between the first and second surfaces;   a doped superjunction region directly adjoining and disposed beneath the gate trench, the doped superjunction region comprising first, second, and third doped pillars, the second pillar laterally centered between the first and third pillars and forming a p-n junction with the first and third pillars,   wherein the first and third doped pillars each comprise a planar uppermost boundary that is substantially parallel to the first surface.   
     
     
         23 . The vertical trenched gate transistor of  claim 22 , wherein the distance between a bottom of the doped superjunction region and the field stop region is greater than 70% of a vertical thickness of the drift region. 
     
     
         24 . The vertical trenched gate transistor of  claim 22 , wherein the distance between a bottom of the doped superjunction region and the field stop region is greater than 90% of a vertical thickness of the drift region. 
     
     
         25 . The vertical trenched gate transistor of  claim 22 , wherein the second doped pillar is an n-type region with a higher doping concentration than the drift region, and wherein the first and third pillars are p-type regions. 
     
     
         26 . The vertical trenched gate transistor of  claim 22 , wherein the planar uppermost boundaries of the first and third pillars are vertically spaced apart from the body region by a portion of the drift region. 
     
     
         27 . The vertical trenched gate transistor of  claim 22 , wherein the first, second and third doped pillars each comprise a lowermost boundary, the lowermost boundary of the first, second and third doped pillars each being vertically spaced apart from the field stop region by substantially the same distance.