Semiconductor Device and Method of Fabricating the Same

Abstract

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom suffice of the first trench.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first interlayer insulating layer including a first trench, on a substrate;   a first liner layer along a side wall and a bottom surface of the first trench and including a noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart;   a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench; and   a capping layer on the top surface of the first metal wire.   
     
     
         2 . The semiconductor device of  claim 1 , wherein at a point where the first liner layer and the top surface of the first metal wire are adjacent to each other, an uppermost surface of the first iffier layer and the top surface of the first metal wire are continuous. 
     
     
         3 . The semiconductor device of  claim 2 , wherein at the point where the first liner layer and the top surface of the first metal wire are adjacent to each other, no step is between the uppermost surface of the first liner layer and the top surface of the first metal wire. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the top surface of the first metal wire comprises a first point and a second point,
 a distance up to the first point from a point where the top surface of the first metal wire and an uppermost surface of the first liner layer meet is less than a distance up to the second point from the point where the top surface of the first metal wire and the uppermost surface of the first liner layer meet, and   a depth up to the first point from the uppermost surface of the first liner layer is less than a depth up to the. second point front the uppermost surface of the first liner layer.   
     
     
         5 . The semiconductor device of  Claim 1 , wherein the noble metal comprises at least one of ruthenium (Ru) platinum (Pt), iridium (Ir), and rhodium (Rh). 
     
     
         6 . The semiconductor device of  claim 1 , wherein the capping layer directly contacts the first liner layer and the first metal wire. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the capping layer does not extend on the top surface of the first interlayer insulating layer. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the capping layer comprises at least, one of cobalt (Co), ruthenium (Ru), and manganese (Mn). 
     
     
         9 . The semiconductor device of  claim 1 , further comprising:
 a first barrier layer along the side wall and the bottom surface of the first trench, between the first interlayer insulating layer and the first liner layer.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the first barrier layer is directly on an upper surface of the substrate. 
     
     
         11 . The conductor device of  claim 10 , further comprising:
 an etch stop layer between the first interlayer insulating layer and the substrate.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the etch stop layer is directly on the upper surface of the substrate. 
     
     
         13 . The semiconductor device of  claim 1 , further comprising:
 a second interlayer insulating layer comprising a second trench, on the first interlayer insulating layer;   a second liner layer along a side wall and a bottom surface of the second trench and including the noble metal; and   a second metal wire filling the second trench and electrically connected with the first metal wire,   wherein a top surface of the second metal wire has a convex shape toward the bottom surface of the second trench.   
     
     
         14 . A semiconductor device, comprising:
 an interlayer insulating layer comprising a trench, on a substrate;   a barrier layer along a side wall and a bottom surface of the trench;   a ruthenium (Ru) liner layer along the side wall and the bottom surface of the trench, on the barrier layer;   a metal wire filling the trench and comprising copper, on the ruthenium liner layer, a top surface of the metal wire having a convex shape toward the bottom surface of the trench and being continuous with an uppermost surface of the ruthenium liner layer; and   a capping layer along the top surface of the metal wire.   
     
     
         15 . The semiconductor device of  claim 14 ,
 wherein the metal wire directly contacts the ruthenium liner layer, and wherein no step is between the uppermost surface of the ruthenium, liner layer and the top surface of the metal wire.   
     
     
         16 . The semiconductor device of  claim 14 , wherein the capping layer is a cobalt (Co) layer. 
     
     
         17 . The semiconductor device of  claim 14 , wherein the interlayer insulating layer comprises a low-dielectric material having a lower dielectric constant than silicon oxide. 
     
     
         18 . A semiconductor device comprising:
 a substrate;   an insulating layer, having a trench therein, on the substrate;   a metal liner layer in the trench;   a metal wire in the trench on the metal liner layer; and   a metal capping layer on the metal wire. wherein a combination of the metal capping layer and the metal liner layer covers four surfaces of the metal wire.   
     
     
         19 . The semiconductor device of  claim 18 ,
 wherein the four surfaces of the metal wire comprise a bottom surface, first and second side surfaces, and a non-planar top surface,   wherein a non-planar portion of the metal capping layer covers the non-planar top surface of the metal wire, and   wherein the metal liner layer covers the bottom surface of the metal wire, and the first and second side surfaces of the metal wire.   
     
     
         20 . The semiconductor device of  claim 19 , further comprising a metal barrier layer in the trench, wherein the metal liner layer is between the metal barrier layer and the metal wire.