Semiconductor Substrate

Abstract

A semiconductor substrate includes a device carrier, a plurality of stiffener structures and a plurality of spaced areas. The device carrier includes a plurality of trace layout units and a periphery around the trace layout units. The stiffener structures are disposed on the device carrier along the periphery of the trace layout units. The spaced areas are disposed between the stiffener structures.

What is claimed is: 
     
         1 . A semiconductor substrate, comprising:
 a device carrier comprising a plurality of trace layout units and a periphery around the trace layout units;   a plurality of stiffener structures disposed on the device carrier along the periphery of the trace layout units; and   a plurality of spaced areas disposed between the stiffener structures.   
     
     
         2 . The semiconductor substrate according to  claim 1 , wherein the device carrier having a first surface and a second surface opposite to the first surface, the plurality of stiffener structures disposed on the first surface of the device carrier. 
     
     
         3 . The semiconductor substrate according to  claim 2 , wherein the plurality of stiffener structures extend on the first surface in a direction away from the second surface to form a cavity with the device carrier. 
     
     
         4 . The semiconductor substrate according to  claim 2 , further comprising:
 a plurality of locking elements disposed below the plurality of stiffener structures and embedded within the device carrier, wherein the plurality of locking elements adjoins the plurality of stiffener structures and extends away from the stiffener structure towards the second surface of the device carrier.   
     
     
         5 . The semiconductor substrate according to  claim 4 , wherein the plurality of locking elements extend from the first surface of the device carrier to the second surface of the device carrier, and exposed on the second surface of the device carrier. 
     
     
         6 . The semiconductor substrate according to  claim 2 , wherein the device carrier comprises at least one conductive layer, wherein the at least one conductive layer connects the first surface of the device carrier to the second surface of the device carrier. 
     
     
         7 . The semiconductor substrate according to  claim 6 , wherein the device carrier comprises a plurality of conductive layers disposed on the different locations of the device carrier. 
     
     
         8 . The semiconductor substrate according to  claim 7 , wherein the plurality of conductive layers comprises:
 a first conductive layer comprising a plurality of traces; and   a second conductive layer comprising a plurality of studs, wherein the plurality of studs are disposed correspondingly on the plurality of traces;   wherein the plurality of traces and studs are embedded in the insulating layer between the first and second surface of the device carrier, the plurality of traces and studs form the plurality of trace layout units.   
     
     
         9 . The semiconductor substrate according to  claim 7 , wherein at least one of plurality of conductive layers is electrically connected to the stiffener structure. 
     
     
         10 . The semiconductor substrate according to  claim 1 , wherein the stiffener structure comprises at least one metallic material. 
     
     
         11 . The semiconductor substrate according to  claim 10 , wherein the stiffener structure further comprises at least one polymeric material disposed between the first surface of the device carrier and the stiffener structure. 
     
     
         12 . The semiconductor substrate according to  claim 1 , wherein the stiffener structure comprises a metallic material and a polymeric material. 
     
     
         13 . The semiconductor substrate according to  claim 1 , wherein the stiffener structure comprises a metallic material and a solderable material. 
     
     
         14 . The semiconductor substrate according to  claim 1 , wherein the stiffener structure comprises a continuous ring-shaped structure. 
     
     
         15 . The semiconductor substrate according to  claim 1 , wherein the stiffener structure comprises a discontinuous ring-shaped structure. 
     
     
         16 . The semiconductor substrate according to  claim 1 , wherein the stiffener structure is disposed on the edge of the semiconductor substrate. 
     
     
         17 . The semiconductor substrate according to  claim 1 , further comprising:
 a plurality of guiding elements disposed on the device carrier in accordance with the spaced areas.   
     
     
         18 . The semiconductor substrate according to  claim 17 , wherein the guiding elements each have at least one portion embedded in the device carrier. 
     
     
         19 . The semiconductor substrate according to  claim 17 , wherein the guiding elements each comprise a first guiding layer and a second guiding layer. 
     
     
         20 . The semiconductor substrate according to  claim 19 , wherein the second guiding layer is a discontinuous guiding layer. 
     
     
         21 . The semiconductor substrate according to  claim 19 , wherein the width of the first guiding layer is larger than the width of the second guiding layer. 
     
     
         22 . The semiconductor substrate according to  claim 17 , wherein the shape of each guiding element is irregular. 
     
     
         23 . The semiconductor substrate according to  claim 17 , wherein the plurality of trace layout units is in the form of array, the plurality of spaced areas forms at least one breaking line between the plurality of trace layout units. 
     
     
         24 . The semiconductor substrate according to  claim 23 , wherein the breaking line is disposed between the stiffener structure and the guiding element. 
     
     
         25 . The semiconductor substrate according to  claim 24 , wherein the semiconductor substrate is separated along the breaking line. 
     
     
         26 . The semiconductor substrate according to  claim 17 , wherein the device carrier comprises:
 at least one insulating layer formed using a molding material.   
     
     
         27 . The semiconductor substrate according to  claim 1 , wherein the semiconductor substrate is separated via the bending mechanism along the spaced area. 
     
     
         28 . The semiconductor substrate according to  claim 1 , wherein the semiconductor substrate is separated via the shear mechanism along the spaced area.