Run-Time Parallelization of Code Execution Based on an Approximate Register-Access Specification

Abstract

A method includes, in a processor ( 20 ) that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. Respective values of the destination registers are made available to a second segment of the instructions only upon verifying that the values are valid for readout by the second segment in accordance with the approximate specification. The second segment is processed at least partially in parallel with processing of the first segment, using the values made available from the first segment.

1 . A method, comprising:
 in a processor that processes instructions of program code, processing a first segment of the instructions;   using an approximate specification that defines register access by the instructions, identifying in the first segment one or more destination registers which the approximate specification defines approximately rather than exactly;   making respective values of the destination registers available to a second segment of the instructions only upon verifying that the values are known to be valid for readout by the second segment, even though the approximate specification is not exact in defining the access to the destination registers; and   processing the second segment at least partially in parallel with processing of the first segment, using the values made available from the first segment.   
     
     
         2 . The method according to  claim 1 , wherein processing the second segment comprises processing at least one instruction in the second segment, which according to the approximate specification does not depend on the values, before the values are made available. 
     
     
         3 . The method according to  claim 1 , wherein verifying that a value of a destination register is valid for readout by the second segment comprises verifying that all conditional branch instructions in the first segment that precede a last write to the destination register are resolved. 
     
     
         4 . The method according to  claim 1 , wherein verifying that a value of a destination register is valid for readout by the second segment comprises verifying that a last write to the destination register has been fully or speculatively committed in the first segment. 
     
     
         5 . The method according to  claim 1 , wherein verifying that the values are valid for readout by the second segment comprises verifying that a last write instruction, to any of the destination registers in the first segment, has been fully or speculatively committed. 
     
     
         6 . The method according to  claim 1 , wherein processing of the second segment is performed without providing at least one of a flow-control trace and a scoreboard to the second segment. 
     
     
         7 . The method according to  claim 1 , wherein processing of the second segment is performed without providing a flow-control trace to the first segment. 
     
     
         8 . The method according to  claim 1 , wherein processing the second segment comprises continuing processing of the second segment regardless of branch mis-prediction occurring in the first segment. 
     
     
         9 . The method according to  claim 1 , and comprising flushing the second segment in response to identifying a violation of the approximate specification by the first segment. 
     
     
         10 . The method according to  claim 9 , wherein the violation comprises writing to a register that, in accordance with the approximate specification, is not to be written to, or writing to a register more times than a number of writes specified for the register in the approximate specification. 
     
     
         11 . The method according to  claim 9 , wherein the violation comprises flushing of the first segment. 
     
     
         12 . The method according to  claim 9 , wherein flushing the second segment in response to the violation is performed only if a value of a destination register causing the violation in the first segment is actually used in the second segment. 
     
     
         13 . The method according to  claim 1 , and comprising flushing the second segment in response to identifying that the first segment failed to reach a predefined location in the program code. 
     
     
         14 . The method according to  claim 13 , wherein identifying that the first segment failed to reach the predefined location comprises detecting that processing of the first segment reached an instruction that is predefined as a parallelization point for invoking one or more subsequent segments. 
     
     
         15 . The method according to  claim 13 , wherein identifying that the first segment failed to reach the predefined location comprises detecting that processing of the first segment has processed more than a predefined amount of the program code. 
     
     
         16 . The method according to  claim 1 , wherein making the values available for readout by the second segment comprises predicting at least one of the values, and, when the at least one of the values becomes valid in accordance with the approximate specification, verifying that the prediction was correct. 
     
     
         17 . The method according to  claim 16 , and comprising flushing the second segment in response to finding that the prediction was incorrect. 
     
     
         18 . A processor, comprising:
 an execution pipeline, which is configured to execute instructions of program code; and   parallelization circuitry, which is configured to:
 invoke a first hardware thread to process a first segment of the instructions; 
 identify in the first segment, using an approximate specification that defines register access by the instructions, one or more destination registers which the approximate specification defines approximately rather than exactly; and 
 make respective values of the destination registers available to a second hardware thread, which processes a second segment of the instructions, only upon verifying that the values are known to be valid for readout by the second segment, even though the approximate specification is not exact in defining the access to the destination registers, so as to process the second segment by the second hardware thread at least partially in parallel with processing of the first segment using the values. 
   
     
     
         19 . The processor according to  claim 18 , wherein the parallelization circuitry is configured to invoke the second thread to process at least one instruction in the second segment, which according to the approximate specification does not depend on the values, before the values are made available. 
     
     
         20 . The processor according to  claim 18 , wherein the parallelization circuitry is configured to verify that a value of a destination register is valid for readout by the second segment, by verifying that all conditional branch instructions in the first segment that precede a last write to the destination register are resolved. 
     
     
         21 - 30 . (canceled)