Source-Gate Region Architecture in a Vertical Power Semiconductor Device

Abstract

A vertical drift metal-oxide-semiconductor (VDMOS) transistor with improved contact to source and body regions, and a method of fabricating the same. A masked ion implant of the source regions into opposite-type body regions defines the locations of body contact regions, which are implanted subsequently with a blanket implant. The surface of the source regions and body contact regions are silicide clad, and an overlying insulator layer deposited and planarized. Contact openings are formed through the planarized insulator layer, within which conductive plugs are formed to contact the metal silicide, and thus the source and body regions of the device. A metal conductor is formed overall to the desired thickness, and contacts the conductive plugs to provide bias to the source and body regions.

1 - 24 . (canceled) 
     
     
         25 . An integrated circuit comprising:
 a semiconductor substrate of a first conductivity type;   an epitaxial layer of the first conductivity type overlying the substrate, the epitaxial layer having a lighter dopant concentration than the substrate;   a plurality of gate electrodes disposed near the surface of the epitaxial layer, and spaced apart from one another;   a plurality of body regions of a second conductivity type disposed into the surface of the epitaxial layer at locations between gate electrodes;   within each body region, first and second source regions of the first conductivity type disposed at the surface of the body region;   within each body region, a body contact region of the second conductivity type disposed at the surface between the first and second source regions;   a metal silicide cladding at the surface of at least a portion of the first and second source regions and the body contact region of each body region;   an insulating layer overlying the gate electrodes, and having a planarized surface;   a plurality of conductive plugs contacting the metal silicide cladding through a contact opening in the insulating layer; and   a metal conductor disposed over the insulating layer and in contact with the plurality of conductive plugs.   
     
     
         26 . A method of fabricating a vertical power device, comprising:
 forming a plurality of gate electrodes spaced apart from one another near a surface of a semiconductor of a first conductivity type;   forming a plurality of body regions of a second conductivity type at the surface, the plurality of body regions spaced apart from one another by locations of the surface underlying the gate electrodes;   forming, into each body region, first and second source regions of the first conductivity type;   forming, into each body region, a body contact region of the second conductivity type at locations between the first and second source regions;   depositing a metal in contact with the source regions and body contact regions;   then heating the metal to form a metal silicide at the surface of the source regions and body contact regions;   depositing an insulator material overall;   planarizing the insulator material;   forming contact openings through the planarized insulator material;   forming a plurality of conductive plugs in the contact openings to be in electrical contact with the metal silicide at the surface of the source regions and body contact regions; and   then forming a metal conductor in electrical contact with the plurality of conductive plugs.   
     
     
         27 . An integrated circuit comprising:
 a semiconductor substrate of a first conductivity type;   a plurality of gate electrodes disposed near a top surface of the substrate, and spaced apart from one another;   a plurality of body regions of a second conductivity type disposed into the surface of the substrate at locations between gate electrodes;   within each body region, first and second source regions of the first conductivity type disposed at the surface of the body region;   within each body region, a body contact region of the second conductivity type disposed at the surface between the first and second source regions;   a metal silicide cladding at the surface of at least a portion of the first and second source regions and the body contact region of each body region;   an insulating layer overlying the gate electrodes, and having a planarized surface;   a plurality of conductive plugs contacting the metal silicide cladding through a contact opening in the insulating layer;   a metal conductor disposed over the insulating layer and in contact with the plurality of conductive plugs; and   a collector region of a second conductivity type at a bottom surface of the substrate, and forming a metallurgical junction with the first conductivity type material of the substrate.