Assignee
D3 Semiconductor LLC
US·12 granted patents·4 pending applications·17 citations·filing 2013–2020
Top patents by PatentIndex Score
16 records- 0185US9755058B2Surface devices within a vertical power deviceD3 Semiconductor LLC·Filed 2016·Granted Sep 5, 2017·4 cites·27 claims
- 0284US9806186B2Termination region architecture for vertical power transistorsD3 Semiconductor LLC·Filed 2015·Granted Oct 31, 2017·4 cites·26 claims
- 0381US9496386B2Device architecture and method for improved packing of vertical field effect devicesD3 Semiconductor LLC·Filed 2015·Granted Nov 15, 2016·2 cites·21 claims
- 0480US9117899B2Device architecture and method for improved packing of vertical field effect devicesD3 Semiconductor LLC·Filed 2013·Granted Aug 25, 2015·3 cites·14 claims
- 0578US10074735B2Surface devices within a vertical power deviceD3 Semiconductor LLC·Filed 2017·Granted Sep 11, 2018·2 cites·17 claims
- 0673US10580884B2Super junction MOS bipolar transistor having drain gapsD3 Semiconductor LLC·Filed 2018·Granted Mar 3, 2020·1 cites·16 claims
- 0768US9117709B2Device architecture and method for precision enhancement of vertical semiconductor devicesD3 Semiconductor LLC·Filed 2013·Granted Aug 25, 2015·1 cites·7 claims
- 0858US9997455B2Device architecture and method for precision enhancement of vertical semiconductor devicesD3 Semiconductor LLC·Filed 2017·Granted Jun 12, 2018·0 cites·13 claims
- 0958US9865727B2Device architecture and method for improved packing of vertical field effect devicesD3 Semiconductor LLC·Filed 2016·Granted Jan 9, 2018·0 cites·24 claims
- 1058US2020026517A1Surface devices within a vertical power deviceD3 Semiconductor LLC·Filed 2018·Application pending·0 cites
- 1158US2020203511A1Super junction mos bipolar transistor and process of manufactureD3 Semiconductor LLC·Filed 2020·Application pending·0 cites
- 1255US9589889B2Device architecture and method for precision enhancement of vertical semiconductor devicesD3 Semiconductor LLC·Filed 2015·Granted Mar 7, 2017·0 cites·14 claims
- 1351US10134890B2Termination region architecture for vertical power transistorsD3 Semiconductor LLC·Filed 2017·Granted Nov 20, 2018·0 cites·6 claims
- 1451US2018174968A1Source-Gate Region Architecture in a Vertical Power Semiconductor DeviceD3 Semiconductor LLC·Filed 2017·Application pending·0 cites
- 1549US9837358B2Source-gate region architecture in a vertical power semiconductor deviceD3 Semiconductor LLC·Filed 2016·Granted Dec 5, 2017·0 cites·18 claims
- 1644US2014264343A1Device architecture and method for temperature compensation of vertical field effect devicesD3 Semiconductor LLC·Filed 2014·Application pending·0 cites
Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →