Super junction mos bipolar transistor and process of manufacture

Abstract

Methods and designs are provided for a vertical power semiconductor switch having an IGBT-with-built-in-diode bottom-side structure combined with a SJMOS topside structure in such a way as to provide fast switching with low switching losses (MOSFET), low on-resistance at low currents (SJMOS), low on-resistance at high currents (IGBT), and high current-density capability (IGBT).

1 . A method of creating a super junction metal oxide semiconductor bipolar transistor on a wafer comprising the steps of:
 choosing a set of processing parameters from the group of:
 a collector doping level; 
 a collector extension depth, 
 a collector doping; 
 a gap width; 
 a gap doping; 
   forming a set of P-columns and N-columns from a topside of the wafer;   forming a MOSFET on the topside of the wafer;   forming an N-type field stop region into a backside of the wafer; and,   forming a P+collector node having at least one N+drain gap in the backside of the wafer.   
     
     
         2 . The method of creating a super junction metal oxide semiconductor bipolar transistor on a wafer of  claim 1  further comprising the further steps of:
 creating a first N-type Epi layer; 
 creating a second N-type Epi layer; 
 patterning the second N-type Epi layer with an implant mask; and, 
 implanting a P-type dopant through the implant mask. 
 
     
     
         3 . The method of creating a super junction metal oxide semiconductor bipolar transistor on a wafer of  claim 1  comprising the further steps of:
 growing an oxide layer on the topside of the wafer; 
 forming a gate portion on the oxide layer; and, 
 implanting a body, a body contact and a set of source dopings in the topside of the wafer. 
 
     
     
         4 . The method of creating a super junction metal oxide semiconductor bipolar transistor on a wafer of  claim 1  further comprising the further steps of:
 implanting the N-type field stop with a blanket implant; 
 patterning the backside of the wafer with a P+collector mask; 
 implanting a P-type material into the backside of the wafer to form a P+collector; 
 implanting an N+drain contact into the backside of the wafer with a blanket implant; 
 annealing the backside of the wafer; and, 
 depositing a blanket metallization on the backside of the wafer in contact with the P+collector and the N+drain contact. 
 
     
     
         5 . The method of creating a super junction metal oxide semiconductor bipolar transistor on a wafer of  claim 1  wherein the step of choosing a set of processing parameters further comprises choosing one set of parameters from the group of: 
       
         
           
                 
                 
                 
                 
                 
                 
                 
               
                     
                     
                 
                     
                     
                   Drain gap 
                     
                     
                     
                   Drawn Drain 
                 
                     
                   Final Drain 
                   n-type 
                   Collector 
                   Collector p- 
                   Total P + 
                   width (Drawn 
                 
                     
                   gap width in 
                   doping in 
                   depth in 
                   type doping 
                   Collector 
                   Gap in P + 
                 
                     
                   micrometers 
                   atoms/cm 3   
                   micrometers 
                   in atoms/cm 3   
                   Width 
                   Collector), 
                 
                     
                   (±10%) 
                   (±10%) 
                   (±10%) 
                   (±10%) 
                   (μm) 
                   (μm) 
                 
                     
                     
                 
                     
                 
                 
                 
                 
                 
                 
                 
                 
               
                   SJMOSBT 1 
                   6.0 
                   7.30 × 10 14   
                   4.1 
                   2.40 × 10 17   
                   18.0 
                   6.0 
                 
                   SJMOSBT 2 
                   5.0 
                   6.80 × 10 14   
                   4.4 
                   2.00 × 10 19   
                   18.0 
                   6.0 
                 
                   SJMOSBT 3 
                   2.5 
                   6.90 × 10 14   
                   4.1 
                   2.40 × 10 17   
                   21.0 
                   3.0 
                 
                   SJMOSBT 4 
                   2.0 
                   6.90 × 10 14   
                   4.4 
                   2.00 × 10 19   
                   21.0 
                   3.0 
                 
                   SJMOSBT 5 
                   1.0 
                   7.20 × 10 14   
                   4.4 
                   2.00 × 10 19   
                   21.6 
                   2.4 
                 
                     
                 
             
                
                
                
                
                
                
                
               
               
                
               
            
             
                
                
                
                
                
                
               
            
           
         
       
     
     
         6 . The method of creating a super junction metal oxide semiconductor bipolar transistor on a wafer of  claim 1  wherein the step of choosing a set of processing parameters further comprises choosing from the group of: 
       
         
           
                 
                 
                 
                 
               
                     
                 
                   Final drain gap width 
                   Drain gap n-type 
                   Collector depth in 
                   Collector p-type 
                 
                   in micrometers 
                   doping in atoms/cm 3   
                   micrometers 
                   doping in atoms/cm 3   
                 
                     
                 
                   1 to 6 
                   10 14  to 10 16   
                   1 to 5 
                   10 17  to 10 19   
                 
                     
                 
             
                
                
                
                
               
               
                
                
               
            
           
         
       
     
     
         7 . A method of constructing vertical semiconductor device comprising:
 providing a top surface;   providing a bottom surface;   providing a super junction metal oxide semiconductor field effect transistor (SJMOSFET) in the top surface; and,   providing a plurality of P+collector regions forming a plurality of integrated gate bipolar transistor (IGBT) devices embedded in the bottom surface.   
     
     
         8 . A method of constructing super junction metal oxide semiconductor bipolar transistor comprising:
 providing a source terminal;   providing a gate terminal;   providing a source portion connected to the source terminal;   providing a body contact portion adjacent the source terminal;   providing an extended p-column beneath the body contact portion;   providing a first n-column adjacent a first side of the extended p-column;   providing a second n-column adjacent a second side of the extended p-column;   providing an n-drift region beneath the extended p-column, the first n-column and the second n-column;   providing an n-type field stop layer beneath the n-drift region;   providing a P+collector layer beneath the n-type field stop;   providing an N+drain gap in the P+collector layer;   providing a drain contact beneath the N+drain gap; and,   whereby the N+drain gap enables low Rds(on) unipolar conduction at a low current density and bipolar conduction at a high current density.   
     
     
         9 . The method of  claim 8  further comprising:
 providing that the extended p-column have a doping of about 7×1015 atoms/cm3; 
 providing that the first n-column and the second n-column have dopings of about 7×1015 atoms/cm3; and, 
 providing that the n-drift region have a doping of about 7×1014 atoms/cm3. 
 
     
     
         10 . The method of  claim 9  further comprising providing that the n-type field stop layer has a doping of between about 1015 and about 1017 atoms/cm3. 
     
     
         11 . The method of  claim 10  further comprising:
 providing that the P+collector have a doping of between about 1017 and about 1019 atoms/cm3; and, 
 providing that the N+drain gap have a doping of between about 1014 and about 1016 atoms/cm3. 
 
     
     
         12 . The method of  claim 8  further comprising providing that the N+drain gap within about 1 to 2 μm of the n-type field stop layer have a doping of between about 1014 and about 1017 atoms/cm3. 
     
     
         13 . The method of  claim 8  further comprising that the extend p-column have a depth of between about 35 μm to about 45 μm and a width of about 3 μm. 
     
     
         14 . The method of  claim 8  further comprising providing that the N-drift region have a depth of between about 4 μm and about 10 μm. 
     
     
         15 . The method of  claim 8  further comprising providing that the n-type field stop have a depth of about 2.5 μm. 
     
     
         16 . The method of  claim 8  further comprising providing that the P+collector layer have a depth of between about 0.1 μm and about 5 μm. 
     
     
         17 . The method of  claim 8  further comprising providing that the N+drain gap have a depth of between about 1 μm and about 5 μm and have a width of between about 0.5 μm to about 8 μm. 
     
     
         18 . The method of  claim 8  further comprising providing that the N+drain gap is positioned beneath the second N-column.