Surface devices within a vertical power device

Abstract

A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.

1 . A semiconductor device comprising:
 a surface device;   a first vertical power device that is controlled by the surface device; and,   an insulator separating the surface device and the vertical power device.   
     
     
         2 . (canceled) 
     
     
         3 . The semiconductor device of  claim 1  wherein:
 the vertical power device is a transistor. 
 
     
     
         4 . The semiconductor device of  claim 1  further comprising a second vertical power device connected in parallel with the first vertical power device. 
     
     
         5 . The semiconductor device of  claim 1  further comprising:
 a first metal layer; 
 a second metal layer; and, 
 wherein the vertical power device is configured so that power flows between the first metal layer and the second metal layer. 
 
     
     
         6 . The semiconductor device of  claim 1  wherein the surface device further comprises:
 a set of analog circuits and a set of digital circuits. 
 
     
     
         7 . The semiconductor device of  claim 1  further comprising:
 a set of metal oxide semiconductor regions; 
 a medium voltage N-type metal oxide semiconductor region; 
 a medium voltage P-type metal oxide semiconductor region; 
 a low voltage N-type metal oxide semiconductor region; and, 
 a low voltage P-type metal oxide semiconductor region. 
 
     
     
         8 . The semiconductor device of  claim 6  further comprising:
 a set of resistors and capacitors that form the set of first analog circuits; 
 one or more of the group of logic gates, memory, processors, state machines, erasable programmable read-only memory, and electrically erasable programmable read-only memory that form the set of digital circuits. 
 
     
     
         9 . A semiconductor device comprising:
 a surface device; and,   a vertical power device insulated from and controlled by the surface device.   
     
     
         10 . The semiconductor device of  claim 9   wherein the vertical power device is one of the group of an insulated gate bipolar transistor, a superjunction metal oxide semiconductor, and a field effect transistor.   
     
     
         11 . The semiconductor device of  claim 9  wherein the surface device further comprises a medium voltage region and a low voltage region. 
     
     
         12 . The semiconductor device of  claim 11  wherein:
 the medium voltage region further comprises an NMOS region and a PMOS region; and, 
 wherein the low voltage region further comprises an NMOS region and a PMOS region. 
 
     
     
         13 . The semiconductor device of  claim 12  further comprising:
 a medium voltage N-type metal oxide semiconductor region; 
 a medium voltage P-type metal oxide semiconductor region; 
 a low voltage N-type metal oxide semiconductor region; and, 
 a low voltage P-type metal oxide semiconductor region. 
 
     
     
         14 . The semiconductor device of  claim 13  further comprising:
 a set of metal oxide semiconductor regions 
 a first subregion of the set of metal oxide semiconductor regions including a set of resistors and capacitors that form an analog circuit; and, 
 a second subregion of the set of metal oxide semiconductor regions that forms one or more logic gates, memory, processors, state machines, erasable programmable read-only memory, and electrically erasable programmable read-only memory. 
 
     
     
         15 . A semiconductor device comprising:
 a surface device;   a vertical power device; and,   wherein the vertical power device is controlled by the surface device.   
     
     
         16 . The semiconductor device of  claim 15  further comprising:
 epitaxial silicon; 
 wherein the surface device is formed on the epitaxial silicon; and, 
 wherein the vertical power device is formed on the epitaxial silicon. 
 
     
     
         17 . The semiconductor device of  claim 15  wherein the surface device further comprises:
 one or more of the group of an N-type MOS (NMOS) transistor, a P-type MOS (PMOS) transistor, a Lateral-Drift MOS (LDMOS) transistor, an NPN bipolar junction transistor (NPN), a PNP bipolar junction transistor (PNP), a floating-gate MOS transistor, a diode, a resistor, a capacitor, an inductor, and a fusible element. 
 
     
     
         18 . The semiconductor device of  claim 15  wherein the surface device further comprises:
 an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a state machine, an analog to digital converter, a digital to analog converter, a gate driver, a temperature sensor, a logic gate, a processor, and any other mixed analog-digital circuit construct. 
 
     
     
         19 . The semiconductor device of  claim 15  further comprising a set of metal oxide semiconductor regions includes one or more of the group of a medium voltage N-type metal oxide semiconductor region, a medium voltage P-type metal oxide semiconductor region, a low voltage N-type metal oxide semiconductor region, and a low voltage P-type metal oxide semiconductor region. 
     
     
         20 . The semiconductor device of  claim 15  further comprising:
 a set of metal oxide semiconductor regions including an interconnecting transistor. 
 
     
     
         21 . The semiconductor device of  claim 15  wherein the surface device and the vertical power device are configured to dissipate heat.