Accommodating engineering change orders in integrated circuit design

Abstract

A method includes receiving a register-transfer-level description and a gate-level description for an integrated circuit design. The gate-level description includes one or more spare latches implemented as reconfigurable latch filler cells. The method further includes receiving an engineering change order, and, responsive to the engineering change order, adding the at least one additional latch to the register-transfer-level description and, for at least one of the at least one additional latch, selecting one of the one or more spare latches in the register-transfer-level description to yield a selected spare latch. The method further includes, for the selected spare latch, identifying a selected reconfigurable latch filler cell in the gate-level description and replacing the selected reconfigurable latch filler cell with an operational latch in the gate-level description. The method further includes finalizing the integrated circuit design. A corresponding computer program product and computer systems are also disclosed.

What is claimed is: 
     
         1 . A computer system comprising:
 one or more processors;   one or more computer readable storage media;   computer program instructions;   said computer program instructions being stored on said one or more computer readable storage media;   said computer program instructions comprising instructions to:   receive a register-transfer-level description and a gate-level description for an integrated circuit design, wherein said gate-level description comprises one or more spare latches implemented as reconfigurable latch filler cells;   receive an engineering change order for said integrated circuit design, wherein said engineering change order requires at least one additional latch;   responsive to said engineering change order, add said at least one additional latch to said register-transfer-level description;   for at least one of said at least one additional latch, select one of said one or more spare latches in said register-transfer-level description to yield a selected spare latch;   for said selected spare latch, identify a selected reconfigurable latch filler cell in said gate-level description;   replace said selected reconfigurable latch filler cell with an operational latch in said gate-level description; and   finalize said integrated circuit design;   wherein at least one said reconfigurable latch filler comprises a scan input connection connected to a scan output connection by a short;   wherein said computer program instructions to replace said selected reconfigurable latch filler cell with an operational latch in said gate-level description comprise instructions to remove said short;   wherein said reconfigurable latch filler cell comprises at least one disconnection from a power rail;   wherein said computer program instructions to replace said selected reconfigurable latch filler cell with an operational latch in said gate-level description comprise instructions to connect said reconfigurable latch filler cell to said power rail;   wherein said reconfigurable latch filler cell comprises at least one disconnection from a clock pin;   wherein said computer program instructions to replace said selected reconfigurable latch filler cell with an operational latch in said gate-level description comprises instructions to connect said reconfigurable latch filler cell to said clock pin;   wherein said computer program instructions further comprise instructions to generate a netlist from said gate-level description, route said engineering change order based on said netlist, and omit re-ordering a scan chain for said integrated circuit design;   wherein said computer program instructions further comprise instructions to identify one or more clock buffers for said integrated circuit design, said one or more clock buffers having been sized for said one or more spare latches, and reduce said one or more clock buffers to an optimized clock buffer size, based on a number of instantiated latches in said integrated circuit design; and   wherein said operational latch is identical in area footprint to an pin-compatible with an originally designed latch.