Low power physical layer driver topologies

Abstract

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level. The dedicated transistor is activated based on a voltage level for driving a second terminal of the three terminals and a voltage level for driving a third terminal of the three terminals.

What is claimed is: 
     
         1 . A method of data transfer, comprising:
 mapping data to a sequence of symbols to be transmitted on a plurality of wires via a plurality of terminals;   encoding the sequence of symbols in three signals, wherein each of the three signals is in one of three phases for each symbol to be transmitted, and wherein the three signals are in different phases from one another during transmission of each symbol;   obtaining a signal to be transmitted via a terminal of the plurality of terminals, wherein the signal is one of the three signals;   driving the terminal by turning on a first transistor when the signal is in a first phase, wherein the terminal is driven towards a first voltage level when the first transistor is turned on;   driving the terminal by turning on a second transistor when the signal is in a second phase, wherein the terminal is driven towards a second voltage level when the second transistor is turned on; and   driving the terminal by turning on a third transistor when the signal is in a third phase, wherein the terminal is driven towards a third voltage level when the third transistor is turned on, and wherein the third transistor is turned on based on a voltage supplied from a voltage regulator that also regulates a voltage supplied to the first transistor.   
     
     
         2 . The method of  claim 1 , wherein the driving the terminal when the signal is in the first phase further includes turning off the second transistor. 
     
     
         3 . The method of  claim 2 , wherein the driving the terminal when the signal is in the first phase further includes turning off the third transistor. 
     
     
         4 . The method of  claim 1 , wherein the driving the terminal when the signal is in the second phase further includes turning off the first transistor. 
     
     
         5 . The method of  claim 4 , wherein the driving the terminal when the signal is in the second phase further includes turning off the third transistor. 
     
     
         6 . The method of  claim 1 , wherein the driving the terminal when the signal is in the third phase further includes turning off the first transistor and the second transistor. 
     
     
         7 . The method of  claim 1 , wherein the third voltage level is within a voltage range bounded by the first voltage level and the second voltage level. 
     
     
         8 . A transmitter, comprising:
 a plurality of terminals driven by line drivers;   a processing circuit configured to:
 map data to a sequence of symbols to be transmitted on a plurality of wires via the plurality of terminals, 
 encode the sequence of symbols in three signals, wherein each of the three signals is in one of three phases for each symbol to be transmitted, and wherein the three signals are in different phases from one another during transmission of each symbol, and 
 obtain a signal to be transmitted via a terminal of the plurality of terminals, wherein the signal is one of the three signals; and 
   a line driver configured to:
 drive the terminal by turning on a first transistor when the signal is in a first phase, wherein the terminal is driven towards a first voltage level when the first transistor is turned on, 
 drive the terminal by turning on a second transistor when the signal is in a second phase, wherein the terminal is driven towards a second voltage level when the second transistor is turned on, and 
 drive the terminal by turning on a third transistor when the signal is in a third phase, wherein the terminal is driven towards a third voltage level when the third transistor is turned on, and wherein the third transistor is turned on based on a voltage supplied from a voltage regulator that also regulates a voltage supplied to the first transistor. 
   
     
     
         9 . The transmitter of  claim 8 , wherein the line driver configured to drive the terminal when the signal is in the first phase is further configured to turn off the second transistor. 
     
     
         10 . The transmitter of  claim 9 , wherein the line driver configured to drive the terminal when the signal is in the first phase is further configured to turn off the third transistor. 
     
     
         11 . The transmitter of  claim 8 , wherein the line driver configured to drive the terminal when the signal is in the second phase is further configured to turn off the first transistor. 
     
     
         12 . The transmitter of  claim 11 , wherein the line driver configured to drive the terminal when the signal is in the second phase is further configured to turn off the third transistor. 
     
     
         13 . The transmitter of  claim 8 , wherein the line driver configured to drive the terminal when the signal is in the third phase is further configured to turn off the first transistor and the second transistor. 
     
     
         14 . The transmitter of  claim 8 , wherein the third voltage level is within a voltage range bounded by the first voltage level and the second voltage level. 
     
     
         15 . An apparatus for data transfer, comprising:
 means for mapping data to a sequence of symbols to be transmitted on a plurality of wires via a plurality of terminals;   means for encoding the sequence of symbols in three signals, wherein each of the three signals is in one of three phases for each symbol to be transmitted, and wherein the three signals are in different phases from one another during transmission of each symbol;   means for obtaining a signal to be transmitted via a terminal of the plurality of terminals, wherein the signal is one of the three signals;   means for driving the terminal by turning on a first transistor when the signal is in a first phase, wherein the terminal is driven towards a first voltage level when the first transistor is turned on;   means for driving the terminal by turning on a second transistor when the signal is in a second phase, wherein the terminal is driven towards a second voltage level when the second transistor is turned on; and   means for driving the terminal by turning on a third transistor when the signal is in a third phase, wherein the terminal is driven towards a third voltage level when the third transistor is turned on, and wherein the third transistor is turned on based on a voltage supplied from a voltage regulator that also regulates a voltage supplied to the first transistor.   
     
     
         16 . The apparatus of  claim 15 , wherein the third voltage level is within a voltage range bounded by the first voltage level and the second voltage level. 
     
     
         17 . A processor-readable storage medium having one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to:
 map data to a sequence of symbols to be transmitted on a plurality of wires via a plurality of terminals;   encode the sequence of symbols in three signals, wherein each of the three signals is in one of three phases for each symbol to be transmitted, and wherein the three signals are in different phases from one another during transmission of each symbol;   obtain a signal to be transmitted via a terminal of the plurality of terminals, wherein the signal is one of the three signals;   drive the terminal by turning on a first transistor when the signal is in a first phase, wherein the terminal is driven towards a first voltage level when the first transistor is turned on;   drive the terminal by turning on a second transistor when the signal is in a second phase, wherein the terminal is driven towards a second voltage level when the second transistor is turned on; and   drive the terminal by turning on a third transistor when the signal is in a third phase, wherein the terminal is driven towards a third voltage level when the third transistor is turned on, and wherein the third transistor is turned on based on a voltage supplied from a voltage regulator that also regulates a voltage supplied to the first transistor.   
     
     
         18 . The processor-readable storage medium of  claim 17 , wherein the third voltage level is within a voltage range bounded by the first voltage level and the second voltage level.