Semiconductor wafer, semiconductor device, and method for manufacturing nitride semiconductor layer

Abstract

According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.

1 .- 26 . (canceled) 
     
     
         27 . A semiconductor device formed on a semiconductor wafer, wherein the semiconductor wafer comprises:
 a substrate having a first surface;   an AlN buffer layer on the first surface of the substrate;   a first layer on the AlN buffer layer, the first layer comprising a first nitride semiconductor comprising Al and Ga;   a second layer on the first layer, the second layer comprising a second nitride semiconductor comprising Ga;   a third layer on the second layer, the third layer comprising a third nitride semiconductor comprising Al, a Ga composition ratio in the third layer being lower than a Ga composition ratio in the second layer;   a fourth layer on the third layer, the fourth layer comprising a fourth semiconductor comprising Al and Ga, a Ga composition ratio in the fourth layer being lower than the Ga composition ratio in the second layer, an Al composition ratio in the fourth layer being lower than an Al composition ratio in the third layer;   an intermediate layer on the fourth layer, the intermediate layer comprising one selected from the group consisting of Si, Mg, and B; and   a fifth layer on the intermediate layer, the fifth layer having a composition same as a composition of the second layer,   the second layer having a compressive strain, the third layer and the fifth layer each having a tensile strain, the third layer having a lattice spacing along a first axis parallel to the first surface, the lattice spacing of the third layer being not less than 0.6% of an unstrained lattice spacing along the first axis of semiconductor having a composition same as a composition of the third layer, and not more than 1.4% of the wistrained lattice spacing along the first axis.   
     
     
         28 . The device to  claim 27 , wherein the substrate has a thermal expansion coefficient less than a thermal expansion coefficient of the fifth layer. 
     
     
         29 . The device to  claim 27 , wherein the intermediate layer comprises one selected from the group consisting of SiN, MgN, and BN. 
     
     
         30 . The device to  claim 27 , wherein the third layer has the tensile strain larger than the tensile strain of the fifth layer. 
     
     
         31 . The device to  claim 27 , wherein the third layer and the fourth layer each have an impurity concentration not more than 1×10 18  cm −3 . 
     
     
         32 . The device to  claim 27 , wherein the intermediate layer has a thickness thinner than a thickness of the third layer. 
     
     
         33 . The device to  claim 27 , wherein the intermediate layer includes multiple parts spaced from each other. 
     
     
         34 . The device to  claim 27 , wherein the intermediate layer has a thickness not less than a 0.2 atom layer and not more than 3 nanometers. 
     
     
         35 . The device to  claim 27 , wherein the third layer has a thickness not less than 2 nanometers and not more than 50 nanometers. 
     
     
         36 . The device to  claim 27 , wherein the fourth layer has an Al composition ratio not less than 0.2 and not more than 0.8. 
     
     
         37 . The device to  claim 27 , wherein the fourth layer has a thickness not less than 10 nanometers and not more than 50 nanometers. 
     
     
         38 . The device to  claim 27 , wherein the second layer has a thickness not less than 100 nanometers and not more than 5 micrometers. 
     
     
         39 . The device to  claim 27 , wherein the fifth layer has a thickness not less than 100 nanometers and not more than 5 micrometers. 
     
     
         40 . The device to  claim 27 , wherein the substrate is one selected from the group consisting of a Si substrate, a SiC substrate, a GaP substrate, and an InP substrate. 
     
     
         41 . The device to  claim 27 , wherein the fifth layer has a dislocation density not more than 2×10 9  cm −2 .