Method for late differential soi thinning for improved fdsoi performance and hci optimization

Abstract

Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.

What is claimed is: 
     
         1 . A device comprising:
 a semiconductor stack including a silicon (Si) layer over an insulator layer over a Si substrate, respectively;   a first replacement metal gate (RMG) stack between first spacers over a first channel area of the Si layer;   a second RMG stack between second spacers over a second channel area of the Si layer, wherein the first channel area is thinner than the second channel area; and   a source/drain (S/D) region adjacent an exposed side of each first and second spacer.   
     
     
         2 . The device according to  claim 1 , comprising:
 a first work-function metal electrode in the first RMG stack.   
     
     
         3 . The device according to  claim 2 , comprising:
 a second work-function metal electrode in the second RMG stack.   
     
     
         4 . The device according to  claim 1 , wherein the Si layer of the first channel area has a thickness of 3 to 8 nm. 
     
     
         5 . The device according to  claim 1 , comprising:
 a core (SG) device and an input/output (EG) device comprising the first and second RMG electrodes, respectively.   
     
     
         6 . The device according to  claim 5 , wherein:
 a threshold-voltage of the SG device is lower than a threshold-voltage of the EG device.   
     
     
         7 . The device according to  claim 1 , wherein the S/D regions comprise epitaxially grown raised S/D regions. 
     
     
         8 . The device according to  claim 1 , wherein the first channel is recessed in the Si layer. 
     
     
         9 . The device according to  claim 1 , wherein the first and second RMG stacks comprise first and second gate oxide layers, respectively, 
     
     
         10 . The device according to  claim 9 , wherein the first gate oxide layer having a thickness less than a thickness of the second gate oxide layer. 
     
     
         11 . A device comprising:
 a semiconductor stack including a silicon (Si) layer over an insulator layer over a Si substrate, respectively;   a first replacement metal gate (RMG) stack between first spacers over a first channel area of the Si layer;   a second RMG stack between second spacers over a second channel area of the Si layer, wherein the first channel area is thinner than the second channel area; and   a source/drain (S/D) region adjacent an exposed side of each first and second spacer,   wherein the first and second RMG electrodes comprise a core (SG) device and an input/output (EG) device, respectively.   
     
     
         12 . The device according to  claim 11 , comprising:
 a first work-function metal electrode in the first RMG stack.   
     
     
         13 . The device according to  claim 12 , comprising:
 a second work-function metal electrode in the second RMG stack.   
     
     
         14 . The device according to  claim 11 , wherein the Si layer of the first channel area has a thickness of 3 to 8 nm. 
     
     
         15 . The device according to  claim 1 , wherein:
 a threshold-voltage of the SG device is lower than a threshold-voltage of the EG device.   
     
     
         16 . The device according to  claim 11 , wherein the S/D regions comprise epitaxially grown raised S/D regions. 
     
     
         17 . The device according to  claim 11 , wherein the first channel is recessed in the Si layer. 
     
     
         18 . The device according to  claim 11 , wherein the first and second RMG stacks comprise first and second gate oxide layers, respectively, 
     
     
         19 . The device according to  claim 18 , wherein the first gate oxide layer having a thickness less than a thickness of the second gate oxide layer. 
     
     
         20 . A device comprising:
 a first replacement metal gate (RMG) stack between first spacers over a first channel area of a Si layer;   a second RMG stack between second spacers over a second channel area of the Si layer, wherein the first channel area is thinner than the second channel area; and   a source/drain (S/D) region adjacent an exposed side of each first and second spacer,   wherein the first and second RMG electrodes comprise a core (SG) device and an input/output (EG) device, respectively.