System in package process flow

Abstract

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

What is claimed is: 
     
         1 . A method comprising:
 (a) connecting an integrated circuit (IC) die to a substrate,
 wherein the substrate comprises a first substrate edge portion, a second substrate edge portion, a third substrate edge portion, and a fourth substrate edge portion, 
 wherein the first substrate edge portion and the second substrate edge portion meet at a first corner of the substrate adjacent to a first corner of the IC die, and 
 wherein the third substrate edge portion and the fourth substrate edge portion meet at a second corner of the substrate adjacent to a second corner of the IC die; 
   (b) placing a first upper die package having a first upper die edge portion and a second upper die edge portion over the IC die, so as to cover and extend beyond the first corner of the IC die;   (c) connecting pads on the first upper die edge portion and the second upper die edge portion to contacts of the first substrate edge portion and the second substrate edge portion;   (d) placing a second upper die package having a third upper die edge portion and a fourth upper die edge portion over the IC die that is partially overlaid by the first upper die package, so as to cover and extend beyond the second corner of the IC die; and   (e) connecting pads on the third upper die edge portion and the fourth upper die edge portion to contacts of the third substrate edge portion and the fourth substrate edge portion.   
     
     
         2 . The method of  claim 1 , wherein the second upper die package is located diagonally from the first upper die package, and wherein the first upper die package and the second upper die package are spaced apart so that neither lies over the other. 
     
     
         3 . The method of  claim 1 , the method further comprising:
 depositing a solder paste on the contacts of the first substrate edge portion and the second substrate edge portion before step (c).   
     
     
         4 . The method of  claim 1 , further comprising:
 placing solder on the contacts of the first substrate edge portion and the second substrate edge portion; and   depositing a solder paste on the solder before step (c).   
     
     
         5 . The method of  claim 4 , wherein the solder is placed on the contacts of the first substrate edge portion and the second substrate edge portion after step (a). 
     
     
         6 . The method of  claim 1 , further comprising placing solder on the contacts of the first substrate edge portion and the second substrate edge portion before step (a). 
     
     
         7 . The method of  claim 5 , further comprising
 applying a molded underfill material around the solder and above the first upper die package.   
     
     
         8 . The method of  claim 7 , wherein an underfill material is deposited between the IC die and the substrate, between steps (a) and (b). 
     
     
         9 . The method of  claim 8 , further comprising depositing a first underfill material between the IC die and the substrate, before applying the molded underfill material around the solder. 
     
     
         10 . The method of  claim 1 , further comprising:
 placing a thermal interface material over the IC die before step (b).   
     
     
         11 . A method comprising:
 (a) connecting at an integrated circuit (IC) die to a substrate, so that a first substrate edge portion, a second substrate edge portion, a third substrate edge portion, and a fourth substrate edge portion of the substrate having contacts thereon extend beyond four edges of the IC die;   (b) placing a first upper die package over the IC die, with the IC die located between the first upper die package and the substrate,   (c) placing a second upper die package over the IC die, the first upper die package and the second upper die package positioned diagonally from each other in a plane and spaced apart so that neither the first upper die package and the second upper die package lies over the other;   (d) connecting pads on a first upper die edge portion and a second upper die edge portion of the first upper die package directly to the contacts of the first substrate edge portion and the second substrate edge portion; and   (e) connecting pads on a third upper die edge portion and a fourth upper die edge portion of the second upper die package to the contacts of the third substrate edge portion and the fourth substrate edge portion.   
     
     
         12 . The method of  claim 11 , wherein step (a) includes connecting the IC die to the substrate using solder, the method further comprising applying a first underfill material around the solder, between steps (a) and (b). 
     
     
         13 . The method of  claim 12 , wherein the step of applying the first underfill material includes depositing the first underfill material between the IC die and the substrate. 
     
     
         14 . The method of  claim 11 , further comprising placing a thermal interface material over the IC die before step (b). 
     
     
         15 . A method comprising:
 (a) flip chip mounting an integrated circuit (IC) die over a substrate, wherein the substrate comprises a first substrate edge portion, a second substrate edge portion, a third substrate edge portion, and a fourth substrate edge portion;   (b) placing a first upper die package over the IC die, so as to cover and extend beyond a first IC die corner of the IC die,   (c) connecting pads on a first upper die portion and a second upper die edge portion of the first upper die package to contacts of the first substrate edge portion and the second substrate edge portion;   (d) placing a second upper die package over the substrate that is partially overlaid by the first upper die package, so as to cover and extend beyond a second corner of the IC die; and   (e) connecting pads on a third upper die edge portion and a fourth upper die edge portion of the second upper die package to contacts on the third substrate edge portion and the fourth substrate edge portion.   
     
     
         16 . The method of  claim 15 , wherein the first upper die package and the second upper die package are positioned diagonally from each other and spaced apart so that neither lies over the other. 
     
     
         17 . The method of  claim 15 , wherein step (a) includes connecting the IC die to the substrate using solder, the method further comprising applying a first underfill material around the solder, between steps (a) and (b), wherein the step of applying the first underfill material includes depositing the first underfill material between the IC die and the substrate. 
     
     
         18 . The method of  claim 15 , wherein the first upper die package and the second upper die package includes two different dies from the group consisting of a general purpose processor, a graphics processor, an audio/video processor, a digital radio receiver, DRAM, SRAM, or flash memory, a communications processor, a global positioning satellite (GPS) receiver, and a power management unit. 
     
     
         19 . The method of  claim 15 , wherein the first upper die package and the second upper die package are wafer level chip scale packages. 
     
     
         20 . The method of  claim 15 , further comprising thinning back surfaces of the first upper die package and the second upper die package after step (e).