Inventor · disambiguated record
Chien-Hsiun Lee
Also filed as: LEE CHIEN-HSIUN · LEE CHIEN-HSUN
44 granted patents·5 pending applications·496 citations·filing 2003–2019
98Inventor score
Files withTAIWAN SEMICONDUCTOR MFG14TAIWAN SEMICONDUCTOR MFG CO LTD7WANG TSUNG-DING5YU CHEN-HUA5LEE CHIEN HSIUN4
Top patents by PatentIndex Score
49 records- 0196US8039315B2Thermally enhanced wafer level packageTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Oct 18, 2011·29 cites·19 claims
- 0296US7838424B2Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etchingTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Nov 23, 2010·84 cites·20 claims
- 0396US7148560B2IC chip package structure and underfill processTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Dec 12, 2006·45 cites·18 claims
- 0495US9105552B2Package on package devices and methods of packaging semiconductor diesYU CHEN-HUA·Filed 2012·Granted Aug 11, 2015·33 cites·20 claims
- 0595US8823180B2Package on package devices and methods of packaging semiconductor diesWANG TSUNG-DING·Filed 2012·Granted Sep 2, 2014·30 cites·18 claims
- 0694US9449941B2Connecting function chips to a package to form package-on-packageTSAI PEI-CHUN·Filed 2011·Granted Sep 20, 2016·44 cites·19 claims
- 0792US7842548B2Fixture for P-through silicon via assemblyTAIWAN SEMCONDUCTOR MFG CO LTD·Filed 2008·Granted Nov 30, 2010·29 cites·9 claims
- 0891US9059109B2Package assembly and method of forming the sameLIN HUNG-JEN·Filed 2012·Granted Jun 16, 2015·15 cites·20 claims
- 0990US7656042B2Stratified underfill in an IC packageTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Feb 2, 2010·17 cites·22 claims
- 1089US8743561B2Wafer-level molded structure for package assemblyWANG TSUNG-DING·Filed 2010·Granted Jun 3, 2014·9 cites·8 claims
- 1189US8426256B2Method of forming stacked-die packagesHSIAO C W·Filed 2010·Granted Apr 23, 2013·21 cites·20 claims
- 1288US9768105B2Rigid interconnect structures in package-on-package assembliesLII MIRNG-JI·Filed 2012·Granted Sep 19, 2017·12 cites·20 claims
- 1387US8658464B2Mold chase design for package-on-package applicationsCHENG JUNG WEI·Filed 2011·Granted Feb 25, 2014·10 cites·18 claims
- 1486US9240387B2Wafer-level chip scale package with re-workable underfillCHEN HSIEN-WEI·Filed 2011·Granted Jan 19, 2016·8 cites·17 claims
- 1586US8703539B2Multiple die packaging interposer structure and methodYU CHEN-HUA·Filed 2012·Granted Apr 22, 2014·7 cites·15 claims
- 1684US8492263B2Protected solder ball joints in wafer level chip-scale packagingWANG CHUNG YU·Filed 2007·Granted Jul 23, 2013·11 cites·13 claims
- 1782US8652939B2Method and apparatus for die assemblySUNG MING-CHUNG·Filed 2011·Granted Feb 18, 2014·6 cites·14 claims
- 1882US8334170B2Method for stacking devicesWANG DEAN·Filed 2008·Granted Dec 18, 2012·10 cites·14 claims
- 1981US7026711B2Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA)TAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Apr 11, 2006·33 cites·15 claims
- 2080US9515036B2Methods and apparatus for solder connectionsYU CHEN-HUA·Filed 2012·Granted Dec 6, 2016·4 cites·19 claims
- 2178US8597986B2System in package and method of fabricating sameWANG TSUNG-DING·Filed 2011·Granted Dec 3, 2013·4 cites·20 claims
- 2277US10665565B2Package assemblyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted May 26, 2020·1 cites·20 claims
- 2375US7772691B2Thermally enhanced wafer level packageTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Aug 10, 2010·5 cites·19 claims
- 2472US7491624B2Method of manufacturing low CTE substrates for use with low-k flip-chip package devicesTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Feb 17, 2009·4 cites·15 claims
- 2570US7846769B2Stratified underfill method for an IC packageTAIWAN SEMICONDUCTOR MFG·Filed 2009·Granted Dec 7, 2010·3 cites·19 claims
- 2669US9780064B2Method of forming package assemblyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Oct 3, 2017·1 cites·20 claims
- 2769US8987605B2Formation of connectors without UBMWANG TSUNG-DING·Filed 2011·Granted Mar 24, 2015·2 cites·19 claims
- 2869US8932906B2Through silicon via bonding structureWANG DEAN·Filed 2008·Granted Jan 13, 2015·4 cites·20 claims
- 2969US7573138B2Stress decoupling structures for flip-chip assemblyTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Aug 11, 2009·4 cites·10 claims
- 3068US10163877B2System in package process flowWANG TSUNG DING·Filed 2011·Granted Dec 25, 2018·2 cites·20 claims
- 3163US8169076B2Interconnect structures having lead-free solder bumpsLII MIRNG-JI·Filed 2009·Granted May 1, 2012·2 cites·20 claims
- 3262US10777431B2Post-passivation interconnect structure and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Sep 15, 2020·0 cites·20 claims
- 3362US8664039B2Methods and apparatus for alignment in flip chip bondingSUNG MING-CHUNG·Filed 2011·Granted Mar 4, 2014·1 cites·17 claims
- 3462US8551813B2Wafer level IC assembly methodLEE CHIEN HSIUN·Filed 2012·Granted Oct 8, 2013·1 cites·20 claims
- 3560US7170159B1Low CTE substrates for use with low-k flip-chip package devicesTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jan 30, 2007·1 cites·15 claims
- 3658US10192848B2Package assemblyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jan 29, 2019·0 cites·20 claims
- 3757US7977155B2Wafer-level flip-chip assembly methodsTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Jul 12, 2011·1 cites·5 claims
- 3855US8174114B2Semiconductor package structure with constraint stiffener for cleaning and underfilling efficiencyLEE CHIEN-HSIUN·Filed 2005·Granted May 8, 2012·3 cites·8 claims
- 3952US10453815B2Methods and apparatus for solder connectionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Oct 22, 2019·0 cites·20 claims
- 4052US2018350706A1System in package process flowTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Application pending·0 cites
- 4151US8247267B2Wafer level IC assembly methodLEE CHIEN HSIUN·Filed 2008·Granted Aug 21, 2012·0 cites·10 claims
- 4249US2013127049A1Method for Stacking Devices and Structure ThereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2012·Application pending·0 cites
- 4343US8232183B2Process and apparatus for wafer-level flip-chip assemblyLEE CHIEN-HSIUN·Filed 2007·Granted Jul 31, 2012·0 cites·14 claims
- 4441US2006170088A1Spacer Structures for Semiconductor Package DevicesTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 4541US2013241058A1Wire Bonding Structures for Integrated CircuitsYU CHEN-HUA·Filed 2012·Application pending·0 cites
- 4639US9905520B2Solder ball protection structure with thick polymer layerYU CHEN HUA·Filed 2011·Granted Feb 27, 2018·0 cites·3 claims
- 4739US7851916B2Strain silicon wafer with a crystal orientation (100) in flip chip BGA packageTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Dec 14, 2010·0 cites·20 claims
- 4839US7833896B2Aluminum cap for reducing scratch and wire-bond bridging of bond padsTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Nov 16, 2010·0 cites·14 claims
- 4937US2006170114A1Novel method for copper wafer wire bondingSU CHAO-YUAN·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →