Semiconductor device

Abstract

A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first standard cell and a second standard cell, each of the first standard cell and the second standard cell including:
 a first active region and a second active region, the first active region having a first conductivity type that is different than a second conductivity type of the second active region; 
 a plurality of active patterns on each of the first active region and the second active region and extending in a first direction; 
 device isolation layers filling trenches between the plurality of active patterns and extending in the first direction; and 
 a plurality of gate electrodes on the first active region and the second active region and crossing the plurality of active patterns in a second direction intersecting the first direction; 
   a first diffusion barrier pattern disposed at a boundary between the first standard cell and the second standard cell; and   a second diffusion barrier pattern disposed in the second standard cell, a first depth of the first diffusion barrier pattern being greater than a second depth of the second diffusion barrier pattern,   wherein the second diffusion barrier pattern extends in the second direction parallel to an adjacent one of the plurality of gate electrodes, and   wherein a first pitch between the second diffusion barrier pattern and the adjacent one of the plurality of gate electrodes in the first direction is substantially equal to a second pitch between a pair of the plurality of gate electrodes on the first diffusion barrier pattern.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first pitch is a first distance between a first central line of the second diffusion barrier pattern and a second central line of the adjacent one of the plurality of gate electrodes, and
 wherein the second pitch is a second distance between central lines of the pair of the plurality of gate electrodes.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the first active region is a PMOSFET region, and
 wherein the second active region is an NMOSFET region.   
     
     
         4 . The semiconductor device of  claim 1 , wherein a first width of the first diffusion barrier pattern is greater than a second width of the second diffusion barrier pattern. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a first power pattern and a second power pattern,
 wherein the first power pattern and the second power pattern extend in the first direction and cross the first standard cell and the second standard cell, and   wherein the first power pattern and the second power pattern are connected to the second standard cell.   
     
     
         6 . The semiconductor device of  claim 1 , wherein the first diffusion barrier pattern is a double diffusion barrier pattern, and
 wherein the second diffusion barrier pattern is a single diffusion barrier pattern.   
     
     
         7 . The semiconductor device of  claim 6 , wherein the double diffusion barrier pattern and the single diffusion barrier pattern comprise a silicon oxide layer. 
     
     
         8 . A semiconductor device comprising:
 a first standard cell and a second standard cell, each of the first standard cell and the second standard cell including:
 a first active region and a second active region, the first active region having a first conductivity type that is different than a second conductivity type of the second active region; 
 a plurality of active patterns on each of the first active region and the second active region and extending in a first direction; 
 device isolation layers filling trenches between the plurality of active patterns and extending in the first direction; and 
 a plurality of gate electrodes on the first active region and the second active region and crossing the plurality of active patterns in a second direction intersecting the first direction; 
   a first diffusion barrier pattern disposed at a boundary between the first standard cell and the second standard cell; and   a pair of second diffusion barrier patterns disposed at the boundary, a first depth of the first diffusion barrier pattern being greater than a second depth of the pair of second diffusion barrier patterns,   wherein the pair of second diffusion barrier patterns extend in the second direction from the first diffusion barrier pattern, and   wherein a first pitch between the pair of second diffusion barrier patterns is substantially equal to a second pitch between a pair of the plurality of gate electrodes adjacent to each other in the first direction.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the first pitch is a first distance between central lines of the pair of second diffusion barrier patterns, and
 wherein the second pitch is a second distance between central lines of the pair of the plurality of gate electrodes.   
     
     
         10 . The semiconductor device of  claim 8 , wherein the first active region is a PMOSFET region, and
 wherein the second active region is an NMOSFET region.   
     
     
         11 . The semiconductor device of  claim 8 , wherein a first width of the first diffusion barrier pattern is greater than a second width of each of the pair of second diffusion barrier patterns. 
     
     
         12 . The semiconductor device of  claim 8 , further comprising a first power pattern and a second power pattern,
 wherein the first power pattern and the second power pattern extend in the first direction and cross the first standard cell and the second standard cell, and   wherein the first power pattern and the second power pattern are connected to the second standard cell.   
     
     
         13 . The semiconductor device of  claim 8 , wherein the first diffusion barrier pattern is a double diffusion barrier pattern, and
 wherein each of the pair of second diffusion barrier patterns is a single diffusion barrier pattern.   
     
     
         14 . The semiconductor device of  claim 8 , wherein a first of the pair of second diffusion barrier patterns is aligned with a first side of the first diffusion barrier pattern,
 wherein a second of the pair of second diffusion barrier patterns is aligned with a second side of the first diffusion barrier pattern, and   wherein the second side is opposite to the first side.   
     
     
         15 . A semiconductor device comprising:
 a first standard cell and a second standard cell, each of the first standard cell and the second standard cell including:
 a first active pattern and a second active pattern, the first active pattern and the second active pattern extending in a first direction; 
 device isolation layers disposed at both sides of each of the first active pattern and the second active pattern, the device isolation layers extending in the first direction; and 
 a plurality of gate electrodes crossing the first active pattern and the second active pattern in a second direction intersecting the first direction; 
   a first diffusion barrier pattern disposed at a boundary between the first standard cell and the second standard cell; and   a second diffusion barrier pattern disposed in the second standard cell, a first depth of the first diffusion barrier pattern being greater than a second depth of the second diffusion barrier pattern,   wherein the first active pattern includes a first source/drain region between the second diffusion barrier pattern and an adjacent one of the plurality of gate electrodes,   wherein the second active pattern includes a second source/drain region between the first diffusion barrier pattern and the adjacent one of the plurality of gate electrodes, and   wherein the first source/drain region has a first conductivity type that is different than a second conductivity type of the second source/drain region.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the first conductivity type is a P type, and
 wherein the second conductivity type is an N type.   
     
     
         17 . The semiconductor device of  claim 15 , wherein a first width of the first diffusion barrier pattern is greater than a second width of the second diffusion barrier pattern. 
     
     
         18 . The semiconductor device of  claim 15 , further comprising a first power pattern and a second power pattern,
 wherein the first power pattern and the second power pattern extend in the first direction and cross the first standard cell and the second standard cell,   wherein the first power pattern is electrically connected to the first source/drain region, and   wherein the second power pattern is electrically connected to the second source/drain region.   
     
     
         19 . The semiconductor device of  claim 15 , wherein the first diffusion barrier pattern is a double diffusion barrier pattern, and
 wherein the second diffusion barrier pattern is a single diffusion barrier pattern.   
     
     
         20 . The semiconductor device of  claim 19 , wherein the double diffusion barrier pattern and the single diffusion barrier pattern comprise a silicon oxide layer.