Connector interface for processor packaging

Abstract

An apparatus is provided which comprises: a processor substrate extended away from a processor die, wherein the processor substrate has at least one signal interface which is connectable to a connector; and an interposer coupled to the processor substrate and a motherboard. Described is an apparatus which comprises: a processor substrate extended away from a processor die, wherein the processor substrate has at least one signal interface; and a motherboard coupled to the processor substrate, wherein the motherboard is configured to have a hole which is large enough to place a connector at least partially in it to couple with the at least one signal interface.

1 - 24 . (canceled) 
     
     
         25 . An apparatus comprising:
 a processor substrate extended away from a processor die, wherein the processor substrate includes at least one signal interface which is connectable to a connector; and   an interposer coupled to the processor substrate and a motherboard.   
     
     
         26 . The apparatus of  claim 25 , wherein the interposer is configured to lift the processor substrate and the processor die away from the motherboard such that the connector can connect with the signal interface. 
     
     
         27 . The apparatus of  claim 25 , wherein the connector comprises a Linear Edge Connector (LEC). 
     
     
         28 . The apparatus of  claim 25 , wherein the connector comprises a right-angle connector. 
     
     
         29 . The apparatus of  claim 28 , wherein the interposer comprises a reflow grid array (RGA). 
     
     
         30 . The apparatus of  claim 28 , wherein the RGA has heat traces to distribute heat uniformly in the RGA. 
     
     
         31 . The apparatus of  claim 30 , wherein the processor substrate comprises a substrate of a ball grid array (BGA). 
     
     
         32 . An apparatus comprising:
 a processor substrate extended away from a processor die, wherein the processor substrate includes at least one signal interface; and   a motherboard coupled to the processor substrate, wherein the motherboard is configured to have a hole which is large enough to place a connector at least partially in it to couple with the at least one signal interface.   
     
     
         33 . The apparatus of  claim 32 , comprises an interposer between the motherboard and the processor substrate. 
     
     
         34 . The apparatus of  claim 33 , wherein the connector comprises a Linear Edge Connector (LEC). 
     
     
         35 . The apparatus of  claim 34 , wherein the connector comprises a right-angle connector. 
     
     
         36 . The apparatus of  claim 35 , wherein the processor substrate comprises a substrate of a ball grid array (BGA). 
     
     
         37 . A system comprising:
 a memory;   a processor die coupled to the memory;   a package encasing the processor die, the package including:
 a processor substrate extended away from the processor die, wherein the processor substrate includes at least one signal interface which is connectable to a connector; and 
 an interposer coupled to the processor substrate and a motherboard; and 
   a wireless interface for allowing the processor to communicate with another device.   
     
     
         38 . The system of  claim 37 , wherein the interposer is configured to lift the processor substrate and the processor die away from the motherboard such that a connector can connect with the signal interface. 
     
     
         39 . The system of  claim 37 , wherein the connector comprises a Linear Edge Connector (LEC). 
     
     
         40 . The system of  claim 37 , wherein the connector comprises a right-angle connector. 
     
     
         41 . The system of  claim 37 , wherein the interposer comprises a reflow grid array (RGA). 
     
     
         42 . The system of  claim 41 , wherein the RGA includes heat traces to distribute heat uniformly in the RGA. 
     
     
         43 . The system of  claim 37 , wherein the processor substrate comprises a substrate of a ball grid array (BGA).