Device Package with Reduced Radio Frequency Losses

Abstract

A device package includes a semiconductor device. The semiconductor device is disposed on a substrate. The device package further includes a covering. The covering is disposed on the substrate and surrounds the semiconductor device. The covering includes a void, a first layer, and a second layer. The void is between an interior surface of the covering and the semiconductor device. The first layer has a first electrical conductivity and a first thickness. The second layer is disposed under the first layer. The second layer has a second electrical conductivity and a second thickness. The first electrical conductivity is greater than the second electrical conductivity. The first thickness is less than the second thickness.

1 . A device package comprising:
 a semiconductor device disposed on a substrate; and   a covering disposed on the substrate and surrounding the semiconductor device, the covering comprising
 a void between an interior surface of the covering and the semiconductor device, 
 a first layer comprising a first electrical conductivity and a first thickness, and 
 a second layer disposed under the first layer, the second layer comprising a second electrical conductivity and a second thickness, wherein the first electrical conductivity is greater than the second electrical conductivity, and wherein the first thickness is less than the second thickness. 
   
     
     
         2 . The device package of  claim 1 , wherein the covering is configured to conduct an induced electrical current, and wherein a majority of the induced electrical current is configured to flow in the first layer of the covering. 
     
     
         3 . The device package of  claim 2 , wherein less than 1% of the induced electrical current is configured to flow in the second layer of the covering. 
     
     
         4 . The device package of  claim 1 , further comprising:
 an integrated circuit chip disposed on the substrate, wherein the semiconductor device comprises a sensor; and   an opening vertically aligned with the sensor, wherein the sensor is configured to interact with a region outside the device package through the opening.   
     
     
         5 . The device package of  claim 4 , wherein the opening is disposed in the substrate beneath the sensor. 
     
     
         6 . The device package of  claim 4 , wherein the opening is disposed in the covering above the sensor. 
     
     
         7 . The device package of  claim 4 , wherein the sensor is a microelectromechanical systems (MEMS) device. 
     
     
         8 . The device package of  claim 7 , wherein the MEMS device comprises a MEMS microphone. 
     
     
         9 . The device package of  claim 1 , wherein the covering further comprises
 a third layer disposed over the first layer, the third layer comprising an exterior exposed surface, and   a fourth layer disposed under the second layer, the fourth layer comprising an interior exposed surface, wherein each of the third layer and the fourth layer comprise a corrosion resistant material.   
     
     
         10 . The device package of  claim 9 , wherein each of the third layer and the fourth layer comprise a nickel phosphorus layer and a gold layer, and wherein the exterior exposed surface and the interior exposed surface comprise gold. 
     
     
         11 . The device package of  claim 1 , wherein the first layer comprises copper and the second layer comprises brass. 
     
     
         12 . A method of forming a device package, the method comprising:
 attaching a semiconductor device to a substrate;   forming a covering by
 forming a first layer over a second layer, wherein a conductivity of the first layer is greater than a conductivity of the second layer, and wherein a thickness of the first layer is less than a thickness of the second layer; 
 mechanically shaping the covering to a cup-shaped structure comprising an opening; and 
   attaching the covering to the substrate with the semiconductor device, wherein the semiconductor device is disposed in the opening.   
     
     
         13 . The method of  claim 12 , wherein forming the first layer over the second layer comprises plating a material onto a surface of the second layer. 
     
     
         14 . The method of  claim 13 , wherein the plating is an electroless plating process. 
     
     
         15 . The method of  claim 12 , wherein forming the first layer over the second layer comprises using a chemical deposition process, or sputtering. 
     
     
         16 . The method of  claim 12 , wherein the first layer comprises a metal foil, and wherein forming the first layer over the second layer comprises laminating the metal foil onto a surface of the second layer. 
     
     
         17 . The method of  claim 12 , further comprising:
 attaching an integrated circuit chip to the substrate, wherein the opening surrounds the integrated circuit chip; and   electrically coupling the integrated circuit chip to the substrate.   
     
     
         18 . The method of  claim 12 , further comprising:
 forming a through substrate opening in the substrate, the through substrate opening extending from a first major surface of the substrate to a second major surface of the substrate, wherein the semiconductor device comprises a sensor, wherein the through substrate opening is beneath the sensor and vertically aligned with the sensor, and wherein the sensor is configured to interact with a region outside the device package through the through substrate opening.   
     
     
         19 . The method of  claim 18 , wherein the semiconductor device comprises a microelectromechanical systems (MEMS) device. 
     
     
         20 . The method of  claim 19 , wherein the MEMS device comprises a MEMS microphone. 
     
     
         21 . The method of  claim 12 , further comprising:
 forming a third layer comprising an exterior exposed surface over the first layer; and   forming a fourth layer comprising an interior exposed surface under the second layer, wherein each of the third layer and the fourth layer comprise a corrosion resistant material.   
     
     
         22 . The method of  claim 21 , wherein each of the third layer and the fourth layer comprise a nickel phosphorus layer and a gold layer, and wherein the exterior exposed surface and the interior exposed surface comprise gold. 
     
     
         23 . The method of  claim 12 , wherein the first layer comprises copper and the second layer comprises brass. 
     
     
         24 . A device package comprising:
 a multilayer protective covering comprising
 a core layer for mechanically supporting the multilayer protective covering, the core layer comprising a first thickness less than 200 μm, 
 an electrically conductive layer disposed over a first surface of the core layer, the electrically conductive layer comprising a second thickness less than 20 μm, wherein the multilayer protective covering is indented to comprise a recessed region, wherein the core layer surrounds the recessed region, 
 a corrosion resistant layer disposed over the electrically conductive layer, and 
 a metal layer disposed over the corrosion resistant layer. 
   
     
     
         25 . The device package of  claim 24 , wherein:
 the core layer comprises a first type of brass,   the electrically conductive layer comprises a second type of brass,   an electrical conductivity of the second type of brass is greater than an electrical conductivity of the first type of brass, and   the second thickness is less than about 10 μm.   
     
     
         26 . The device package of  claim 24 , wherein:
 the core layer comprises one of brass or nickel silver;   the first thickness is about 100 μm;   the electrically conductive layer comprises copper; and   the second thickness is between about 3 μm to 6 μm.   
     
     
         27 . The device package of  claim 24 , further comprising:
 a thermally insulating layer disposed under a second surface of the core layer, the second surface being opposite the first surface.   
     
     
         28 . The device package of  claim 27 , further comprising:
 a second corrosion resistant layer disposed under the core layer; and   a second metal layer disposed between the second corrosion resistant layer and the thermally insulating layer.   
     
     
         29 . The device package of  claim 24 , further comprising:
 a finishing layer disposed under the core layer, the corrosion resistant layer and the finishing layer comprising nickel and phosphorus, wherein a thickness of the finishing layer is between about 0.2 μm to about 3 μm.   
     
     
         30 . The device package of  claim 24 , wherein the metal layer comprises gold.