Apparatus and method for triggered prefetching to improve i/o and producer-consumer workload efficiency

Abstract

An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line.

What is claimed is: 
     
         1 . A processor comprising:
 a first core comprising a first cache to store a first set of cache lines;   a second core comprising a second cache to store a second set of cache lines;   a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache;   a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache from a cache of the first core in response to an invalidate command detected for the first cache line.   
     
     
         2 . The processor as in  claim 1  further comprising:
 execution logic to execute a deferred prefetch instruction to cause the prefetch circuit to store the first prefetch request entry in the prefetch request buffer. 
 
     
     
         3 . The processor as in  claim 2  wherein the first prefetch request entry comprises an invalidate address associated with the first cache line, wherein an address associated with the invalidate command is to be compared with the invalidate address and, if a match is found, then the prefetch circuit to cause the first cache line to be prefetched to the second cache. 
     
     
         4 . The processor as in  claim 1  wherein the first core is to acquire a lock on the first cache line and modify the first cache line prior to the invalidate command being generated. 
     
     
         5 . The processor as in  claim 4  wherein the first core releases the lock upon completing modifications to the first cache line, the modifications to the first cache line causing the invalidate command to be generated to invalidate the first cache line in the second cache. 
     
     
         6 . The processor as in  claim 5  wherein the second core is to acquire the lock on the first cache line after receipt of the invalidate command. 
     
     
         7 . The processor as in  claim 1  wherein the first cache line is to be prefetched from a last level cache (LLC) or a system memory. 
     
     
         8 . A processor comprising:
 an I/O interface circuit to access a first set of cache lines in a first cache;   a core comprising a second cache to store a second set of cache lines;   a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the I/O interface circuit;   a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache from the first cache in response to an invalidate command detected for the first cache line.   
     
     
         9 . The processor as in  claim 8  wherein the I/O interface circuit comprises a network interface controller (NIC) and wherein the first cache comprises a last level cache (LLC). 
     
     
         10 . The processor as in  claim 8  further comprising:
 execution logic to execute a deferred prefetch instruction to cause the prefetch circuit to store the first prefetch request entry in the prefetch request buffer. 
 
     
     
         11 . The processor as in  claim 10  wherein the first prefetch request entry comprises an invalidate address associated with the first cache line, wherein an address associated with the invalidate command is to be compared with the invalidate address and, if a match is found, then the prefetch circuit to cause the first cache line to be prefetched to the second cache. 
     
     
         12 . The processor as in  claim 8  wherein the I/O interface circuit is to acquire a lock on the first cache line and modify the first cache line prior to the invalidate command being generated. 
     
     
         13 . The processor as in  claim 12  wherein the first core releases the lock upon completing modifications to the first cache line, the modifications to the first cache line causing the invalidate command to be generated to invalidate the first cache line in the second cache. 
     
     
         14 . The processor as in  claim 13  wherein the second core is to acquire the lock on the first cache line after receipt of the invalidate command. 
     
     
         15 . The processor as in  claim 9  wherein the first cache line is to be prefetched from the LLC and stored in a mid-level cache (MLC) of the core. 
     
     
         16 . A method comprising:
 maintaining coherency between one or more cache lines in a first cache associated with a first core and a second cache associated with a second core, wherein maintaining coherency includes allocating a lock on a first cache line to the first cache;   storing a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line in a prefetch buffer;   detecting an invalidate command for the first cache line; and   in response to detecting the invalidate command for the first cache line, causing the first cache line to be prefetched to a cache associated with a second core from a cache of a first core.   
     
     
         17 . The method as in  claim 16  further comprising:
 executing a deferred prefetch instruction to store the first prefetch request entry in the prefetch request buffer. 
 
     
     
         18 . The method as in  claim 17  wherein the first prefetch request entry comprises an invalidate address associated with the first cache line, wherein an address associated with the invalidate command is to be compared with the invalidate address and, if a match is found, then the prefetch circuit to cause the first cache line to be prefetched to the second cache. 
     
     
         19 . The method as in  claim 16  further comprising:
 acquiring a lock on the first cache line by the first core; and 
 modifying the first cache line prior to the invalidate command being generated. 
 
     
     
         20 . The method as in  claim 19  further comprising:
 releasing, by the first core, the lock upon completing modifications to the first cache line, the modifications to the first cache line causing the invalidate command to be generated to invalidate the first cache line in the second cache. 
 
     
     
         21 . The method as in  claim 20  further comprising:
 acquiring the lock on the first cache line, by the second core, after receipt of the invalidate command. 
 
     
     
         22 . The method as in  claim 16  wherein the first cache line is to be prefetched from a last level cache (LLC) or a system memory.