US2019006382A1PendingUtilityA1

Semiconductor device

Assignee: RENESAS ELECTRONICS CORPPriority: Sep 18, 2015Filed: Jul 25, 2018Published: Jan 3, 2019
Est. expirySep 18, 2035(~9.1 yrs left)· nominal 20-yr term from priority
H01L 27/11573H01L 29/42344H01L 27/11565H01L 2029/7857H01L 29/792H01L 29/7851H10D 30/69H10D 30/62H10D 30/795H10D 30/6219H10D 30/6218H10D 30/6217H10D 30/6211H10D 30/696H10B 41/30H10B 41/20H10B 43/10H10B 41/00H10B 43/40
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Claims

Abstract

A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A manufacturing method of a semiconductor device comprising:
 a projecting portion projecting from an upper surface of a semiconductor substrate in a direction vertical to the upper surface, having a width in a first direction of the upper surface, and extending in a second direction orthogonal to the first direction;   an element isolation film being in contact with the projecting portion and positioned over the upper surface of the semiconductor substrate so as to surround a lower portion of the projecting portion;   a first gate electrode arranged in a first region above the upper surface of the semiconductor substrate and extending in the first direction over the projecting portion and the element isolation film; and   a second gate electrode arranged in a second region different from the first region above the upper surface of the semiconductor substrate and extending in the first direction over the projecting portion and the element isolation film,   the manufacturing method including the steps of:   (a) preparing the semiconductor substrate having the projecting portion and the element isolation film;   (b) forming the first gate electrode over a side surface of the projecting portion via a first gate insulation film in the first region;   (c) depositing a first insulation film so as to cover the projecting portion and then removing the first insulation film formed over the projecting portion and the first gate electrode, and forming a pad insulation film formed of the first insulation film over the element isolation film in the second region;   (d) forming a second gate insulation film having a charge accumulation layer over the side surfaces of the projecting portion and the pad insulation film in the second region; and   (e) forming the second gate electrode above the second gate insulation film formed over the side surfaces of the projecting portion and above the element isolation film in the second region.   
     
     
         2 . The manufacturing method according to  claim 1 ,
 wherein in the step (c), the step of removing the first insulation film formed over the projecting portion and the first gate electrode is performed by isotropic etching.   
     
     
         3 . The manufacturing method according to  claim 1 ,
 wherein the first insulation film comprises silicon oxide.   
     
     
         4 . The manufacturing method according to  claim 1 ,
 wherein the second gate insulation film comprises a silicon oxide film, a silicon nitride film and a silicon oxynitride film.   
     
     
         5 . The manufacturing method according to  claim 4 ,
 wherein the silicon nitride film is formed over the silicon oxide film and the pad insulation film.   
     
     
         6 . The manufacturing method according to  claim 1 ,
 wherein a first overlap length by which the second gate electrode overlaps with the side surfaces of the projecting portion is smaller than a second overlap length by which the first gate electrode overlaps with the side surfaces of the projecting portion in a direction vertical to the upper surface.   
     
     
         7 . A manufacturing method of a semiconductor device comprising:
 (a) preparing a semiconductor substrate having a first projecting portion projecting from an upper surface thereof in a vertical direction and formed in a first region above the upper surface, a second projecting portion formed in a second region different from the first region, a first element isolation film being in contact with a lower portion of the first projecting portion and surrounding the first projecting portion, and a second element isolation film being in contact with a lower portion of the second projecting portion and surrounding the second projecting portion;   (b) forming a first insulation film having a charge accumulation layer over the first projecting portion, the first element isolation film, the second projecting portion and the second element isolation film;   (c) depositing a second insulation film over the first insulation film and then etching the second insulation film, and forming a pad insulation film formed of the second insulation film above the first element isolation film and the second element isolation film;   (d) forming a third insulation film over the first projecting portion, the pad insulation film above the first element isolation film, the second projecting portion, and the pad insulation film above the second element isolation film;   (e) removing the third insulation film and the second insulation film in the second region;   (f) forming a first conductor film over the third insulation film in the first region; and   (g) forming a second conductor film over the second projecting portion via a fourth insulation film in the second region.   
     
     
         8 . The manufacturing method according to  claim 7 ,
 wherein the step (e) includes a step of removing the first insulation film in the second region.   
     
     
         9 . The manufacturing method according to  claim 8 ,
 wherein the step (e) is performed in a condition that the third insulation film is formed over the first projecting portion.   
     
     
         10 . The manufacturing method according to  claim 7 ,
 wherein a first overlap length by which the first conductor film overlaps with side surfaces of the first projecting portion is smaller than a second overlap length by which the second conductor film overlaps with side surfaces of the second projecting portion in a direction vertical to the upper surface.   
     
     
         11 . A manufacturing method of a semiconductor device comprising:
 (a) preparing a semiconductor substrate having a first projecting portion projecting from an upper surface thereof in a vertical direction and formed in a first region above the upper surface, and a second projecting portion formed in a second region different from the first region;   (b) forming a first element isolation film being in contact with a lower portion of the first projecting portion and surrounding the first projecting portion, and a second element isolation film being in contact with a lower portion of the second projecting portion and surrounding the second projection portion;   (c) forming a first insulation film having a charge accumulation layer over the first projecting portion and the first element isolation film;   (d) forming a second insulation film over the first insulation film, and then forming a first conductor film over the second insulation film; and   (e) forming a third insulation film over the second projecting portion, and then forming a second conductor film over the third insulation film,   wherein the first element isolation film is thicker than the second element isolation film.   
     
     
         12 . The manufacturing method according to  claim 11 ,
 wherein a first overlap length by which the first conductor film overlaps with side surfaces of the first projecting portion is smaller than a second overlap length by which the second conductor film overlaps with side surfaces of the second projecting portion in a direction vertical to the upper surface.   
     
     
         13 . The manufacturing method according to  claim 11 ,
 wherein the step (b) includes:   (b1) forming an isolation film in the first region and the second region; and   (b2) removing a part of the isolation film in the second region, thereby forming the second element isolation film formed of the isolation film,   wherein the isolation film in the first region is the first element isolation film.   
     
     
         14 . The manufacturing method according to  claim 13 ,
 wherein the step (b2) is performed in a condition that the isolation film in the first region is covered with a resist film.

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