Technologies for interleaving memory across shared memory pools

Abstract

Technologies for interleaving memory that is accessible via a shared memory pool include a memory sled. The memory sled includes a memory pool of byte-addressable memory devices. The memory sled also includes a memory pool controller coupled to the memory pool. The memory pool controller receives a request to allocate memory addresses of the memory pool to a compute sled. The memory pool controller determines an interleaving configuration for the compute sled as a function of memory characteristics of the compute sled and configures the memory addresses according to the determined interleaving configuration.

1 . A memory sled, comprising:
 a memory pool comprising one or more byte-addressable memory devices;   a memory pool controller coupled to the memory pool, wherein the memory pool controller is to: (i) receive a request to allocate a plurality of memory addresses of the memory pool to a compute sled, (ii) determine an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices, and (iii) configure the one or more memory addresses of the memory pool according to the determined interleaving configuration.   
     
     
         2 . The memory sled of  claim 1 , wherein to determine the interleaving configuration for the compute sled comprises to:
 determine a processor bandwidth and one or more quality of service (QoS) targets associated with the compute sled; and   identify, as a function of the determination of the processor bandwidth and the QoS targets, one or more memory channels connecting with the one or more memory devices to interleave.   
     
     
         3 . The memory sled of  claim 2 , wherein to configure the plurality of memory addresses of the memory pool comprises to expose an address space that includes the one or more memory addresses. 
     
     
         4 . The memory sled of  claim 3 , wherein each of the one or more memory addresses corresponds to an interleaving of the identified one or more memory channels connecting with the one or more memory devices. 
     
     
         5 . The memory sled of  claim 1 , wherein the memory pool controller is further to send a notification, to a compute device, in response to the request to allocate the plurality of memory addresses of the memory pool. 
     
     
         6 . The memory sled of  claim 1 , wherein the memory pool controller is further to:
 receive, from the compute sled, a command to write to the one or more memory addresses configured according to the determined interleaving configuration; and   write, in response to the command, to the one or more memory addresses.   
     
     
         7 . The memory sled of  claim 1 , wherein the memory pool controller is further to:
 receive, from the compute sled, a command to read from the one or more memory addresses configured according to the determined interleaving configuration; and   read, in response to the command, from the one or more memory addresses.   
     
     
         8 . The memory sled of  claim 1 , wherein the interleaved access is to a subset of the one or more memory devices of the memory pool. 
     
     
         9 . The memory sled of  claim 1 , wherein the memory pool controller is further to:
 receive, from an orchestrator server, a modification of the determined interleaving configuration.   
     
     
         10 . The memory sled of  claim 9 , wherein the modification of the interleaving configuration is determined as a function of a QoS target. 
     
     
         11 . The memory sled of  claim 9 , wherein the modification is indicative of an addition of one or more of the memory devices to the interleaving configuration. 
     
     
         12 . The memory sled of  claim 11 , wherein the memory pool controller is further to configure one or more additional memory addresses of the memory pool according to the modification of the determined interleaving configuration, wherein each of the one or more additional memory addresses corresponds to an interleaving of additional memory channels connecting with the one or more memory devices. 
     
     
         13 . The memory sled of  claim 9 , wherein the modification is indicative of a removal of one or more of the memory devices from the interleaving configuration. 
     
     
         14 . One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a memory sled to:
 receive a request to allocate a plurality of memory addresses of a memory pool to a compute sled, wherein the memory pool includes one or more byte-addressable memory devices,   determine an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices; and   configure the one or more memory addresses of the memory pool according to the determined interleaving configuration.   
     
     
         15 . The one or more non-transitory machine-readable storage media of  claim 14 , wherein to determine the interleaving configuration for the compute sled comprises to:
 determine a processor bandwidth and one or more quality of service (QoS) targets associated with the compute sled; and   identify, as a function of the determination of the processor bandwidth and the QoS targets, one or more memory channels connecting with the one or more memory devices to interleave.   
     
     
         16 . The one or more non-transitory machine-readable storage media of  claim 15 , wherein to configure the plurality of memory addresses of the memory pool comprises to expose an address space that includes the one or more memory addresses. 
     
     
         17 . The one or more non-transitory machine-readable storage media of  claim 16 , wherein each of the one or more memory addresses corresponds to an interleaving of the identified one or more memory channels connecting with the one or more memory devices. 
     
     
         18 . The one or more non-transitory machine-readable storage media of  claim 14 , wherein the plurality of instructions further cause the memory sled to send a notification, to a compute device, in response to the request to allocate the plurality of memory addresses of the memory pool. 
     
     
         19 . The one or more non-transitory machine-readable storage media of  claim 14 , wherein the plurality of instructions further cause the memory sled to:
 receive, from the compute sled, a command to write to the one or more memory addresses configured according to the determined interleaving configuration; and   write, in response to the command, to the one or more memory addresses.   
     
     
         20 . The one or more non-transitory machine-readable storage media of  claim 14 , wherein the plurality of instructions further cause the memory sled to:
 receive, from the compute sled, a command to read from the one or more memory addresses configured according to the determined interleaving configuration; and   read, in response to the command, from the one or more memory addresses.   
     
     
         21 . The one or more non-transitory machine-readable storage media of  claim 14 , wherein the interleaved access is to a subset of the one or more memory devices of the memory pool. 
     
     
         22 . A method comprising:
 receiving, by a memory sled, a request to allocate a plurality of memory addresses of a memory pool to a compute sled, wherein the memory pool includes one or more byte-addressable memory devices,   determining, by the memory sled, an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices; and   configuring, by the memory sled, the one or more memory addresses of the memory pool according to the determined interleaving configuration.   
     
     
         23 . The method of  claim 22 , wherein determining the interleaving configuration for the compute sled comprises:
 determining a processor bandwidth and one or more quality of service (QoS) targets associated with the compute sled; and   identifying, as a function of the determination of the processor bandwidth and the QoS targets, one or more memory channels connecting with the one or more memory devices to interleave.   
     
     
         24 . The method of  claim 23 , wherein configuring the plurality of memory addresses of the memory pool comprises exposing an address space that includes the one or more memory addresses. 
     
     
         25 . A system comprising:
 a compute sled; and   a memory sled coupled to the compute sled, wherein the memory sled includes:
 a memory pool comprising one or more byte-addressable memory devices; 
 a memory pool controller coupled to the memory pool, wherein the memory pool controller is to: (i) receive a request to allocate a plurality of memory addresses of the memory pool to the compute sled, (ii) determine an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices, and (iii) configure the one or more memory addresses of the memory pool according to the determined interleaving configuration.