Inventor · disambiguated record
Dimitrios Ziakas
Also filed as: ZIAKAS DIMITRIOS
25 granted patents·8 pending applications·207 citations·filing 2011–2025
95Inventor score
Top patents by PatentIndex Score
33 records- 0198US10476670B2Technologies for providing remote access to a shared memory poolINTEL CORP·Filed 2017·Granted Nov 12, 2019·18 cites·25 claims
- 0298US10469252B2Technologies for efficiently managing allocation of memory in a shared memory poolINTEL CORP·Filed 2017·Granted Nov 5, 2019·17 cites·25 claims
- 0397US11245604B2Techniques to support multiple interconnect protocols for a common set of interconnect connectorsINTEL CORP·Filed 2020·Granted Feb 8, 2022·3 cites·24 claims
- 0497US9317429B2Apparatus and method for implementing a multi-level memory hierarchy over common memory channelsRAMANUJAN RAJ K·Filed 2011·Granted Apr 19, 2016·92 cites·39 claims
- 0594US9600416B2Apparatus and method for implementing a multi-level memory hierarchyRAMANUJAN RAJ K·Filed 2011·Granted Mar 21, 2017·23 cites·31 claims
- 0694US9378133B2Autonomous initialization of non-volatile random access memory in a computer systemNACHIMUTHU MURUGASAMY K·Filed 2011·Granted Jun 28, 2016·32 cites·21 claims
- 0789US10581596B2Technologies for managing errors in a remotely accessible memory poolINTEL CORP·Filed 2017·Granted Mar 3, 2020·2 cites·25 claims
- 0887US9832876B2CPU package substrates with removable memory mechanical interfacesINTEL CORP·Filed 2014·Granted Nov 28, 2017·7 cites·36 claims
- 0982US10719443B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2019·Granted Jul 21, 2020·2 cites·19 claims
- 1080US10241912B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2017·Granted Mar 26, 2019·2 cites·32 claims
- 1178US2025349327A1Stacked memory chip solution with reduced package inputs/outputs (i/os)INTEL CORP·Filed 2025·Application pending·0 cites
- 1274US10586764B2Semiconductor package with programmable signal routingINTEL CORP·Filed 2016·Granted Mar 10, 2020·2 cites·20 claims
- 1373US9361257B2Mechanism for facilitating customization of multipurpose interconnect agents at computing devicesZIAKAS DIMITRIOS·Filed 2011·Granted Jun 7, 2016·4 cites·20 claims
- 1473US2018025299A1Automated data center maintenanceKUMAR MOHAN J·Filed 2017·Application pending·0 cites
- 1572US10884195B2Techniques to support multiple interconnect protocols for a common set of interconnect connectorsINTEL CORP·Filed 2016·Granted Jan 5, 2021·0 cites·25 claims
- 1670US2019042408A1Technologies for interleaving memory across shared memory poolsINTEL CORP·Filed 2018·Application pending·0 cites
- 1769US12505065B2On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHYINTEL CORP·Filed 2023·Granted Dec 23, 2025·0 cites·20 claims
- 1866US9507534B2Home agent multi-level NVM memory architectureZIAKAS DIMITRIOS·Filed 2011·Granted Nov 29, 2016·2 cites·19 claims
- 1964US12340863B2Stacked memory chip solution with reduced package inputs/outputs (I/Os)INTEL CORP·Filed 2021·Granted Jun 24, 2025·0 cites·19 claims
- 2061US10146657B2Initialization trace of a computing deviceSWANSON ROBERT C·Filed 2014·Granted Dec 4, 2018·1 cites·25 claims
- 2152US12282366B2System, apparatus and methods for power communications according to a CXL power protocolINTEL CORP·Filed 2021·Granted Apr 22, 2025·0 cites·20 claims
- 2252US9015388B2Controlling access to storage in a computing deviceINTEL CORP·Filed 2013·Granted Apr 21, 2015·0 cites·20 claims
- 2351US12380005B2Failover for pooled memoryINTEL CORP·Filed 2021·Granted Aug 5, 2025·0 cites·15 claims
- 2449US11036642B2Architectural enhancements for computing systems having artificial intelligence logic disposed locally to memoryINTEL CORP·Filed 2019·Granted Jun 15, 2021·0 cites·17 claims
- 2549US10331614B2Method and apparatus for server platform architectures that enable serviceable nonvolatile memory modulesINTEL CORP·Filed 2013·Granted Jun 25, 2019·0 cites·10 claims
- 2649US2018007791A1Cpu package substrates with removable memory mechanical interfacesINTEL CORP·Filed 2017·Application pending·0 cites
- 2748US10176108B2Accessing memory coupled to a target node from an initiator nodeINTEL CORP·Filed 2016·Granted Jan 8, 2019·0 cites·18 claims
- 2844US2019042511A1Non volatile memory module for rack implementationsINTEL CORP·Filed 2018·Application pending·0 cites
- 2944US2019042162A1Back-end memory channel that resides between first and second dimm slots and applications thereofINTEL CORP·Filed 2018·Application pending·0 cites
- 3043US10211120B2Rework grid array interposer with direct powerINTEL CORP·Filed 2015·Granted Feb 19, 2019·0 cites·21 claims
- 3142US2020228630A1Persistence service for edge architecturesINTEL CORP·Filed 2020·Application pending·0 cites
- 3241US9256493B2Memory module architectureNACHIMUTHU MURUGASAMY K·Filed 2011·Granted Feb 9, 2016·0 cites·23 claims
- 3337US2016093377A1Nonvolatile memory moduleINTEL CORP·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →