Method for Forming a PN Junction and Associated Semiconductor Device

Abstract

An integrated circuit includes an insulating layer overlying a semiconductor substrate. A semiconductor layer of a first conductivity type overlies the insulating layer. A plurality of projecting regions that are spaced apart from each other overly the semiconductor layer. A sequence of PN junctions are in the semiconductor layer. Each PN junction is located at an edge of an associated projecting region. Each PN junction also extends vertically from an upper surface of the semiconductor layer to the insulating layer.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 a semiconductor substrate;   an insulating layer overlying the semiconductor substrate;   a semiconductor layer of a first conductivity type overlying the insulating layer;   a plurality of projecting regions that are spaced apart from each other overlying the semiconductor layer; and   a sequence of PN junctions in the semiconductor layer, each PN junction located at an edge of an associated projecting region and vertically extending from an upper surface of the semiconductor layer to the insulating layer.   
     
     
         2 . The integrated circuit according to  claim 1 , wherein the plurality of projecting regions comprises disconnected strips extending along a top surface of the semiconductor layer, the disconnected strips being parallel to each other. 
     
     
         3 . The integrated circuit according to  claim 1 , wherein the sequence of PN junctions forms a plurality of diodes, each diode including a heavily doped region of the first conductivity type that abuts a lightly doped region of the first conductivity type that abuts a doped region of a second conductivity type. 
     
     
         4 . The integrated circuit according to  claim 3 , wherein some of the diodes form a current bridge rectifier. 
     
     
         5 . The integrated circuit according to  claim 4 , wherein the current bridge rectifier comprises a Graetz bridge. 
     
     
         6 . The integrated circuit according to  claim 1 , wherein the sequence of PN junctions comprises first areas of a second conductivity type overdoped relative to other portions of the semiconductor layer, and second areas of the first conductivity type overdoped relative to the other portions of the semiconductor layer, a first area lying between two second areas and separated from these two second areas by two interleaved regions of the semiconductor layer located, respectively, under two neighboring projecting regions, each junction between a first area and an interleaved region forming a diode, wherein the first areas comprise P+ doped areas that form anodes of the diodes, and wherein the second areas comprise N+ doped areas that, together with the interleaved regions, form cathodes of the diodes. 
     
     
         7 . The integrated circuit according to  claim 1 , wherein the semiconductor layer is a polysilicon layer. 
     
     
         8 . The integrated circuit according to  claim 1 , wherein each of the plurality of projecting regions comprises a layer of dielectric and a gate material overlying the layer of dielectric. 
     
     
         9 . The integrated circuit according to  claim 1 , further comprising floating gate transistors laterally spaced from the sequence of PN junctions, each floating gate transistor comprising a floating gate and a control gate, wherein the semiconductor layer is located at the same level as the floating gates of the floating gate transistors, and the plurality of projecting regions is located at the same level as the control gates of the floating gate transistors. 
     
     
         10 . An integrated circuit comprising:
 a semiconductor substrate;   an insulating layer overlying the semiconductor substrate;   a semiconductor layer overlying the insulating layer;   a plurality of projecting regions that are spaced apart from each other overlying the semiconductor layer;   a plurality of interleaved regions disposed within the semiconductor layer, each interleaved region being located beneath an associated projecting region and being lightly doped with dopants of a first conductivity type;   a plurality of first areas disposed within the semiconductor layer, each first area abutting an associated interleaved region at a location near a first edge of the associated projecting region, each first area being heavily doped with dopants of the first conductivity type and extending from an upper surface of the semiconductor layer to the insulating layer; and   a plurality of second areas disposed within the semiconductor layer, each second area abutting an associated interleaved region at a location near a second edge of the associated projecting region, each second area being heavily doped with dopants of a second conductivity type and extending from the upper surface of the semiconductor layer to the insulating layer.   
     
     
         11 . The integrated circuit according to  claim 10 , wherein the plurality of projecting regions comprises disconnected strips extending along a top surface of the semiconductor layer, the disconnected strips being parallel to each other. 
     
     
         12 . The integrated circuit according to  claim 10 , wherein the interleaved regions, the plurality of first areas, and the plurality of second areas form diodes that are connected to form a current bridge rectifier. 
     
     
         13 . The integrated circuit according to  claim 10 , further comprising floating gate transistors laterally spaced from the plurality of projecting regions, each floating gate transistor comprising a floating gate and a control gate, wherein the semiconductor layer is located at the same level as the floating gates of the floating gate transistors, and the plurality of projecting regions are located at the same level as the control gates of the floating gate transistors. 
     
     
         14 . The integrated circuit according to  claim 10 , wherein the semiconductor layer is a polysilicon layer. 
     
     
         15 . The integrated circuit according to  claim 10 , wherein each of the plurality of projecting regions comprises a layer of dielectric and a gate material overlying the layer of dielectric. 
     
     
         16 . An integrated circuit comprising:
 a semiconductor substrate;   an insulating layer overlying the semiconductor substrate;   a first semiconductor region having a first conductivity type overlying the insulating layer, wherein the first semiconductor region has a first doping concentration;   a second semiconductor region having the first conductivity type overlying the insulating layer, the second semiconductor region abutting the first semiconductor region, wherein the second semiconductor region has a second doping concentration that is less than the first doping concentration;   a third semiconductor region having a second conductivity type overlying the insulating layer, the third semiconductor region abutting the second semiconductor region, wherein the second conductivity type is opposite the first conductivity type;   a first PN junction at a first interface between the third semiconductor region and the second semiconductor region;   a first conductive material overlying and electrically contacting the first semiconductor region;   a second conductive material overlying and electrically insulated from the second semiconductor region; and   a third conductive material overlying and electrically contacting the third semiconductor region.   
     
     
         17 . The integrated circuit according to  claim 16 , wherein the first conductive material and the third conductive material each comprise a metallic material. 
     
     
         18 . The integrated circuit according to  claim 16 , wherein the second conductive material comprises polysilicon. 
     
     
         19 . The integrated circuit according to  claim 16 , further comprising:
 a fourth semiconductor region having the first conductivity type overlying the insulating layer, the fourth semiconductor region abutting the third semiconductor region, wherein the fourth semiconductor region has a third doping concentration substantially equal to the second doping concentration; and   a second PN junction at a second interface between the fourth semiconductor region and the third semiconductor region.   
     
     
         20 . The integrated circuit according to  claim 19 , further comprising:
 a fourth conductive material overlying and electrically insulated from the fourth semiconductor region.