Utilization Metrics for Processing Engines

Abstract

In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

What is claimed is: 
     
         1 . A processor comprising:
 a plurality of processing engines; and   a power control unit to:
 monitor a first utilization metric for a first processing engine; 
 detect a thread transfer from a first processing engine to a second processing engine; and 
 generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. 
   
     
     
         2 . The processor of  claim 1 , the power control unit to:
 control a power state of the second processing engine using the generated second utilization metric.   
     
     
         3 . The processor of  claim 1 , wherein the detected thread transfer comprises a data hand-off from a first thread executing on the first processing engine to a second thread executing on the second processing engine. 
     
     
         4 . The processor of  claim 3 , further comprising:
 a first thread-specific register associated with the second thread, the first thread-specific register to store an identifier for the first thread.   
     
     
         5 . The processor of  claim 1 , wherein the detected thread transfer comprises a migration of a first thread from the first processing engine to the second processing engine. 
     
     
         6 . The processor of  claim 1 , wherein the second utilization metric is a copy of the first utilization metric. 
     
     
         7 . The processor of  claim 1 , the power control unit to:
 generate the second utilization metric using a combination of a past utilization metric of the second processing engine and the first utilization metric.   
     
     
         8 . The processor of  claim 1 , further comprising:
 a plurality of thread-specific registers, each thread-specific register including a transfer source field and a transfer type field.   
     
     
         9 . A method comprising:
 monitoring, by a power control unit of a processor, a first utilization metric for a first processing engine of the processor;   detecting, by the power control unit, a thread transfer from the first processing engine to a second processing engine; and   generating by the power control unit, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine.   
     
     
         10 . The method of  claim 9 , further comprising:
 controlling a power state of the second processing engine using the generated second utilization metric.   
     
     
         11 . The method of  claim 9 , wherein the detected thread transfer comprises one of a data hand-off between threads and a migration of a single thread. 
     
     
         12 . The method of  claim 9 , further comprising:
 generating the second utilization metric as a copy of the first utilization metric.   
     
     
         13 . The method of  claim 9 , further comprising:
 generating the second utilization metric using a combination of a past utilization metric of the second processing engine and the first utilization metric.   
     
     
         14 . The method of  claim 9 , wherein detecting the thread transfer comprises:
 reading, by the power control unit, a transfer source field of a thread-level register associated with a destination thread of the thread transfer.   
     
     
         15 . The method of  claim 9 , further comprising, prior to reading the transfer source field:
 populating the transfer source field by an operating system.   
     
     
         16 . A system comprising:
 a processor comprising a first processing engine, a second processing engine, and a power control unit to calculate a utilization metric of the second processing engine based on execution of one or more first instructions by the second processing engine in combination with a utilization metric of the first processing engine, wherein the utilization metric of the first processing engine is based on execution of one or more second instructions by the first processing engine, the one or more first instructions and the one or more second instructions corresponding to one or more threads of a single application; and   a system memory coupled to the processor.   
     
     
         17 . The system of  claim 16 , wherein the one or more first instructions correspond to a producer thread and the one or more second instructions correspond to a consumer thread, wherein the producer thread provides data to the consumer thread. 
     
     
         18 . The system of  claim 16 , wherein the one or more first instructions and the one or more second instructions correspond to a single thread that is migrated from the first processing engine to the second first processing engine. 
     
     
         19 . The system of  claim 16 , the power control unit to:
 control a power state of the second processing engine using the utilization metric of the second processing engine.   
     
     
         20 . The system of  claim 16 , further comprising:
 a plurality of thread-specific registers, each thread-specific register including a transfer source field and a transfer type field.