Semiconductor on Insulator Devices Containing Permanent Charge

Abstract

A lateral SOI device may include a semiconductor channel region connected to a drain region by a drift region. An insulation region on the drift layer is positioned between the channel region and the drain region. Permanent charges may be embedded in the insulation region sufficient to cause inversion in the insulation region. The semiconductor layer also overlies a global insulation layer, and permanent charges are preferably embedded in at least selected areas of this insulation layer too.

1 - 6 . (canceled) 
     
     
         7 . A lateral semiconductor-on-insulator device comprising:
 a first-conductivity-type semiconductor body region, electrically connected to a drain region by a second-conductivity-type semiconductor drift region;   a dielectric overlying said drift region between said body and drain regions;   said drift region overlying a buried dielectric layer;   a first-conductivity-type surface region in said drift region, in proximity to an interface between said dielectric and said drift region; and   permanent charge, embedded in said dielectric with a density sufficient to cause depletion in the surface region.   
     
     
         8 . The lateral semiconductor-on-insulator device of  claim 7 , further comprising:
 a bottom region at a junction between said semiconductor-on-insulator region and a insulator layer; and   second permanent charges embedded in said buried dielectric layer with a density sufficient to cause depletion in said bottom region.   
     
     
         9 . The lateral semiconductor-on-insulator device of  claim 7 , further comprising a trench gate. 
     
     
         10 . The lateral semiconductor-on-insulator device of  claim 7 , wherein said body is p-type. 
     
     
         11 . The lateral semiconductor-on-insulator device of  claim 7 , wherein said permanent charge has a density sufficient to cause inversion in said semiconductor-on-insulator region. 
     
     
         12 . The lateral semiconductor-on-insulator device of  claim 7 , further comprising a second-conductivity-type source diffusion surrounded by said body region. 
     
     
         13 . The lateral semiconductor-on-insulator device of  claim 7 , wherein said buried dielectric layer is completely continuous across the device. 
     
     
         14 - 19 . (canceled) 
     
     
         20 . A lateral semiconductor-on-insulator device comprising:
 an n-type source region, separated from a drift region by a p-type body region;
 said drift region separating said body region from a drain region; 
   a dielectric overlying said drift region;   said drift region overlying a buried dielectric layer;   permanent charge, embedded at the interface between said dielectric and said drift region, and having a density at least sufficient to cause inversion of said drift region; and   additional permanent charge, embedded at the interface between said buried dielectric and said drift region, and having a density at least sufficient to cause depletion of at least part of said drift region.   
     
     
         21 . The lateral semiconductor-on-insulator device of  claim 20 , further comprising additional permanent charges embedded in said buried dielectric layer, and wherein said second permanent charges at least partly deplete said drift region. 
     
     
         22 . The lateral semiconductor-on-insulator device of  claim 20 , wherein said permanent charge has a density sufficient to cause inversion in said semiconductor-on-insulator region. 
     
     
         23 . The lateral semiconductor-on-insulator device of  claim 20 , wherein said drift region is partly n-type, and also includes p-type portions in proximity to said permanent charge. 
     
     
         24 . The lateral semiconductor-on-insulator device of  claim 20 , wherein said drift region is n-type. 
     
     
         25 . The lateral semiconductor-on-insulator device of  claim 20 , wherein said drift region includes only a single conductivity type. 
     
     
         26 . The lateral semiconductor-on-insulator device of  claim 20 , further comprising a trench gate which controls conduction through part of said body region. 
     
     
         27 - 35 . (canceled) 
     
     
         36 . A method of operating a lateral semiconductor-on-insulator device comprising:
 in the off state, blocking conduction from a source region through a body region and a drift region to a drain region, by turning off a channel portion of said body region, and allowing applied voltage to deplete at least part of said drift region;   wherein the charge of ionized dopant atoms in depleted portion of said drift region is at least partly balanced by one or more of permanent charge at an interface between said drift region and an overlying dielectric, and   permanent charge at an interface between said drift region and one or more isolation trenches which laterally border said drift region; and   in the ON state, enabling conduction by turning on said channel portion.   
     
     
         37 . The method of  claim 36 , wherein the charge of ionized dopant atoms in depleted portion of said drift region is at least partly balanced by permanent charge at an interface between said drift region and an underlying buried dielectric. 
     
     
         38 . The method of  claim 36 , wherein said drift region comprises both first and second conductivity types. 
     
     
         39 . The method of  claim 36 , wherein said drift region comprises both first and second conductivity types, and wherein said permanent charge has a polarity which inverts the nearest portion of said drift region.