Semiconductor package

Abstract

A semiconductor package may include a first redistribution layer (RDL); a first semiconductor chip on a top surface of the first RDL, the first semiconductor chip including a first circuit surface and a first bottom surface, the first circuit surface having first I/O pads thereon, the first I/O pads configured to electrically connect the first semiconductor chip to the first RDL via first wire bonds; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second circuit surface and a second bottom surface; and a second RDL on the second semiconductor chip, the second RDL facing both the first circuit surface and the second circuit surface.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor package, comprising:
 a first redistribution layer (RDL);   a second RDL being disposed apart from the first RDL in a first direction,   at least one semiconductor chip being disposed between the first RDL and the second RDL; and   a first via and a second via being each connected between the first RDL and the second RDL, the first via and the second via being spaced apart from each other in a second direction, the second direction being perpendicular to the first direction, wherein
 the at least one semiconductor chip is disposed between the first via and the second via, and 
 the at least one semiconductor chip is connected to at least one of the first RDL and the second RDL. 
   
     
     
         22 . The semiconductor package of  claim 21 , wherein the at least one semiconductor chip includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip, wherein
 the first semiconductor chip is electrically connected to the first RDL, and   the second semiconductor chip is electrically connected to the second RDL.   
     
     
         23 . The semiconductor package of  claim 22 , wherein the first semiconductor chip includes a first circuit surface and a first bottom surface, and the second semiconductor chip includes a second circuit surface and a second bottom surface, wherein
 a bottom surface of the second RDL faces both the first circuit surface and the second circuit surface.   
     
     
         24 . The semiconductor package of  claim 23 , wherein the second semiconductor chip further includes contacts on the second circuit surface thereof, the contacts being interposed between the second circuit surface and the second RDL such that the contacts electrically connect the second semiconductor chip to the second RDL. 
     
     
         25 . The semiconductor package of  claim 23 , further comprising:
 a third semiconductor chip disposed between the first RDL and the second bottom surface of the second semiconductor chip such that the third semiconductor chip and the first semiconductor chip have a gap therebetween, the third semiconductor chip including a third circuit surface and a third bottom surface, the third circuit surface facing the second RDL, the third semiconductor chip being electrically connected to the first RDL.   
     
     
         26 . The semiconductor package of  claim 25 , wherein the second semiconductor chip further includes contacts on the second circuit surface thereof, the contacts being interposed between the second circuit surface and the second RDL such that the contacts electrically connect the second semiconductor chip to the second RDL. 
     
     
         27 . The semiconductor package of  claim 25 , further comprising:
 a fourth semiconductor chip in the gap between the first semiconductor chip and the third semiconductor chip, the fourth semiconductor chip including a fourth circuit surface and a fourth bottom surface, the fourth circuit surface facing the first RDL.   
     
     
         28 . The semiconductor package of  claim 27 , wherein the second semiconductor chip further includes contacts on the second circuit surface thereof, the contacts being interposed between the second circuit surface and the second RDL such that the contacts electrically connect the second semiconductor chip to the second RDL. 
     
     
         29 . The semiconductor package of  claim 23 , further comprising:
 an adhesive layer interposed between the first circuit surface of the first semiconductor chip and the second bottom surface of the second semiconductor chip.   
     
     
         30 . The semiconductor package of  claim 22 , wherein the first semiconductor chip has a first width and the second semiconductor chip has a second width different from the first width, each of the first and second widths is a length extending in the second direction. 
     
     
         31 . The semiconductor package of  claim 30 , wherein the first width of the first semiconductor chip is larger than the second width of the second semiconductor chip. 
     
     
         32 . The semiconductor package of  claim 21 , wherein each of the at least one semiconductor chip is electrically connected to a nearest RDL. 
     
     
         33 . A semiconductor package, comprising:
 a first semiconductor package including,
 a first RDL, 
 a first semiconductor chip on a top surface of the first RDL, the first semiconductor chip being electrically connected to the first RDL, 
 a second semiconductor chip on a top surface of the first semiconductor chip, 
 a second RDL on a top surface of the second semiconductor chip, the second RDL being electrically connected to the second semiconductor chip, and 
 a first via and a second via electrically connecting the first RDL and the second RDL; and 
   a second semiconductor package on the top surface of the first semiconductor package, the second semiconductor package including a third semiconductor chip, wherein
 the first semiconductor chip and the second semiconductor chip are disposed between the first via and the second via. 
   
     
     
         34 . The semiconductor package of  claim 33 , wherein the second semiconductor package is electrically connected to the second RDL of the first semiconductor package. 
     
     
         35 . The semiconductor package of  claim 33 , wherein the first semiconductor package further includes an external terminal, the external terminal is disposed a bottom surface of the first RDL and electrically connected to an external device. 
     
     
         36 . The semiconductor package of  claim 33 , wherein
 the first semiconductor chip includes a first circuit surface and a first bottom surface,   the second semiconductor chip includes a second circuit surface and a second bottom surface, wherein
 a bottom surface of the second RDL faces both the first circuit surface and the second circuit surface. 
   
     
     
         37 . The semiconductor package of  claim 36 , wherein the second semiconductor chip further includes contacts on the second circuit surface thereof, the contacts interposed between the second circuit surface and the second RDL such that the contacts electrically connect the second semiconductor chip to the second RDL. 
     
     
         38 . The semiconductor package of  claim 33 , wherein the first semiconductor chip has a first width and the second semiconductor chip has a second width smaller than the first width. 
     
     
         39 . The semiconductor package of  claim 33 , wherein the first semiconductor package further includes a fourth semiconductor chip, the fourth semiconductor chip is disposed between the first RDL and a bottom surface of the second semiconductor chip such that the fourth semiconductor chip and the first semiconductor chip have a gap therebetween, the fourth semiconductor chip includes a third circuit surface and a third bottom surface, the third circuit surface faces the second RDL, the fourth semiconductor chip is electrically connected to the first RDL. 
     
     
         40 . The semiconductor package of  claim 39 , wherein the first semiconductor package further includes a fifth semiconductor chip in the gap between the first semiconductor chip and the fourth semiconductor chip, the fifth semiconductor chip includes a fourth circuit surface and a fourth bottom surface, the fourth circuit surface faces the first RDL, the fifth semiconductor chip is electrically connected to the first RDL.