Three-dimensional semiconductor device

Abstract

A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

What is claimed is: 
     
         1 . A three-dimensional (3D) semiconductor device comprising:
 a substrate including a cell array region and a connection region;   a stack structure including a plurality of stacks vertically stacked on the substrate, each of the stacks having a pad portion disposed in the connection region; and   contact plugs connected to the pad portions of the stacks, respectively,   wherein each of the pad portions of the stacks includes a plurality of electrodes vertically stacked, and   wherein, in at least one of the pad portions of the stacks, sidewalls of the electrodes are horizontally spaced apart from each other between the contact plugs adjacent to each other.   
     
     
         2 . The 3D semiconductor device of  claim 1 , wherein ends of top surfaces of the pad portions of the stacks are horizontally spaced apart from each other by a first distance,
 wherein, in the at least one of the pad portions of the stacks, a sidewall of an uppermost electrode is horizontally spaced apart from a sidewall of a lowermost electrode by a second distance, and   wherein the second distance is less than a half of the first distance.   
     
     
         3 . The 3D semiconductor device of  claim 2 , wherein each of the contact plugs has a width greater than the second distance. 
     
     
         4 . The 3D semiconductor device of  claim 2 , wherein the pad portions include first pad portions and second pad portions,
 wherein a number of the electrodes included in each of the second pad portions is less than a number of the electrodes included in each of the first pad portions, and   wherein, in the first or second pad portion, a sidewall of an uppermost electrode is horizontally spaced apart from a sidewall of a lowermost electrode by the second distance.   
     
     
         5 . The 3D semiconductor device of  claim 1 , wherein, in another of the pad portions of the stacks, sidewalls of the electrodes are vertically aligned with each other. 
     
     
         6 . The 3D semiconductor device of  claim 1 , wherein the stack structure has a sidewall profile of a first stepwise structure defined by the pad portions of the stacks,
 wherein each of the pad portions of the stacks has a sidewall profile of a second stepwise structure defined by the electrodes thereof,   wherein the first stepwise structure has a first inclination angle with respect to a top surface of the substrate,   wherein the first inclination angle is smaller than 90 degrees,   wherein the second stepwise structure has a second inclination angle with respect to the top surface of the substrate, and   wherein the second inclination angle is greater than the first inclination angle and smaller than 90 degrees.   
     
     
         7 . The 3D semiconductor device of  claim 1 , further comprising:
 a plurality of vertical structures penetrating the plurality of stacks in the cell array region; and   a data storage layer disposed between the stack structure and each of the vertical structures.   
     
     
         8 . A 3D semiconductor device, comprising:
 a substrate including a cell array region and a connection region;   a stack structure including a plurality of stacks vertically stacked on the substrate, each of the stacks extending from the cell array region into the connection region, wherein each subsequently higher stack extends a lesser distance into the connection region than the stack below it; and   each stack includes a plurality of electrodes having sidewall and top surfaces with an uppermost electrode extending into the connection region a lesser distance than any other electrode within the stack.   
     
     
         9 . The 3D semiconductor device of  claim 8 , further comprising: a plurality of vertical structures penetrating the stacks in the cell array region; and
 a data storage layer disposed between each of the vertical structures and the stacks.   
     
     
         10 . The 3D semiconductor device of  claim 9 , wherein the device is a vertical NAND (VNAND) device. 
     
     
         11 . The 3D semiconductor device of  claim 9 , wherein the stacked structure includes two stepwise structures, the two stepwise structures including a first stepwise structure defined by the steps of individual stacks within the stack structure and having a first angle with the substrate associated with it and a second stepwise structure defined by the steps of individual electrodes within individual stacks and having a second angle with the substrate associated with it, and the second angle that is different from the first angle. 
     
     
         12 . The 3D semiconductor device of  claim 9 , further comprising:
 a filling insulation layer formed on the substrate to cover the stack structure;   conductive lines formed on top of the filling insulation layer; and   contact plugs connecting the conductive lines to pads associated electrodes within each stack.