Plasma processing apparatus and method for forming semiconductor device structure

Abstract

A plasma processing apparatus is provided. The plasma processing apparatus includes a plasma chamber including a housing, and a first electrode array disposed above and outside the housing. The first electrode array includes a plurality of first sub-electrodes. The plasma processing apparatus also includes a number of first matching units outside of the housing, and each of the first matching units is electrically connected to each of the first sub-electrodes.

What is claimed is: 
     
         1 . A plasma processing apparatus, comprising:
 a plasma chamber comprising a housing and a wafer support;   a first electrode array disposed over the wafer support, wherein the first electrode array comprises a plurality of first sub-electrodes; and   a plurality of first matching units connected to the first electrode array, wherein each of the first matching units is electrically connected to each of the first sub-electrodes.   
     
     
         2 . The plasma processing apparatus as claimed in  claim 1 , further comprising:
 a first RF power source connected to the plurality of first sub-electrodes configured to provide energy to the plurality of first sub-electrodes via the plurality of first matching units.   
     
     
         3 . The plasma processing apparatus as claimed in  claim 1 , further comprising:
 a wafer support disposed in the plasma chamber; and   a second electrode array disposed in the wafer support, wherein the second electrode array comprises a plurality of second sub-second electrodes.   
     
     
         4 . The plasma processing apparatus as claimed in  claim 3 , further comprising:
 a plurality of second matching units connected to the plurality of second sub-electrodes, wherein each of the second matching units is electrically connected to one of the plurality of second sub-electrodes.   
     
     
         5 . The plasma processing apparatus as claimed in  claim 4 , further comprising:
 a second RF power source connected to the plurality of second sub-electrodes configured to provide energy to the plurality of second sub-electrodes via the plurality of second matching units.   
     
     
         6 . The plasma processing apparatus as claimed in  claim 3 , wherein each of the plurality of first sub-electrodes and the plurality of second sub-electrodes comprises aluminum (Al), nickel (Ni), chromium (Cr), tin (Sn), copper (Cu), platinum (Pt), gold (Au), ceramic or piezoelectric material. 
     
     
         7 . The plasma processing apparatus as claimed in  claim 1 , wherein each of the first sub-electrodes has a distance which is measured from a top surface of the housing to a bottom surface of each of the plurality of first sub-electrodes, and the first sub-electrodes have the same or different heights. 
     
     
         8 . The plasma processing apparatus as claimed in  claim 1 , wherein the first electrode array further comprises an insulating material insulates the adjacent sidewalls of the plurality of first sub-electrodes. 
     
     
         9 . The plasma processing apparatus as claimed in  claim 1 , wherein the plurality of first sub-electrodes is arranged in a spiral shape when seen from a top-view. 
     
     
         10 . The plasma processing apparatus as claimed in  claim 1 , further comprising:
 a plurality of gas channels disposed in the wafer support, wherein the gas channels are disposed above the second electrode array;   an electrostatic electrode disposed in the wafer support; and   a cooling plate disposed in the wafer support, wherein the electrostatic electrode is between the gas channels and the cooling plate.   
     
     
         11 . A plasma processing apparatus, comprising:
 a plasma chamber comprising a housing and a wafer support;   a top electrode array disposed over the wafer support, wherein the top electrode array comprises a plurality of top sub-electrodes spaced apart from one another; and   a bottom electrode array disposed in the wafer support, wherein the bottom electrode comprises a plurality of bottom sub-electrodes spaced apart from one another.   
     
     
         12 . The plasma processing apparatus as claimed in  claim 11 , further comprising:
 a plurality of top matching units each electrically connected to one of the plurality of top sub-electrodes; and   a first RF power source configured to provide energy to the top sub-electrodes via the plurality of top matching units.   
     
     
         13 . The plasma processing apparatus as claimed in  claim 11 , further comprising:
 a plurality of gas channels disposed in the wafer support, wherein the plurality of gas channels is positioned above the bottom electrode array; and   an electrostatic electrode disposed in the wafer support, wherein the electrostatic electrode is positioned above the bottom electrode array.   
     
     
         14 . The plasma processing apparatus as claimed in  claim 13 , further comprising:
 a plurality of bottom matching units each electrically connected to one of the plurality of bottom sub-electrodes.   
     
     
         15 . The plasma processing apparatus as claimed in  claim 11 , wherein two adjacent ones of the plurality of top sub-electrodes are separated from each other by a dielectric layer. 
     
     
         16 . The plasma processing apparatus as claimed in  claim 11 , wherein the top electrode array further comprises an insulating material insulates the adjacent sidewalls of the top sub-electrodes. 
     
     
         17 . A method for forming a semiconductor device structure, comprising:
 placing in a plasma chamber a substrate including a material layer thereon, wherein the plasma chamber comprises:
 a housing; 
 a first electrode array comprising a plurality of first sub-electrodes; 
 a plurality of first matching units each electrically connected to one of the plurality of first sub-electrodes; and 
 a second electrode array disposed in the housing, the second electrode array comprising a plurality of second sub-electrodes; 
   supplying an etching gas into the plasma chamber;   applying a first RF power source to the first sub-electrodes of the first electrode array by each of the first matching units to form an etching plasma from the etching gas,   adjusting a distance between each of the first sub-electrodes and the substrate to generate a plasma density distribution across the substrate; and   performing an etching process on the material layer using the etching plasma.   
     
     
         18 . The method of  claim 17 , further comprising:
 applying a second RF power source to the plurality of second sub-electrodes of the second electrode array by a plurality of second matching units, wherein the plurality of second sub-electrodes is configured to increase the plasma density near the material layer.   
     
     
         19 . The method of  claim 18 , further comprising:
 supplying a cleaning gas into the plasma chamber;   performing a cleaning process on an edge region of the substrate by applying the first RF power source to a portion of the plurality of first sub-electrodes which is located at an edge region of the first electrode array to increase the plasma density near the edge region of the substrate.   
     
     
         20 . The method of  claim 17 , wherein the etching plasma has different plasma density in different regions above the substrate.