Reconstituted wafer structure

Abstract

A reconstituted wafer includes a plurality of apertures defined in a first substrate. A module is positioned in each aperture and coupled to circuit traces on the first substrate by operation of beam leads extending from the module. A second substrate is positioned over the first substrate and each module is hermetically sealed in a space defined by the respective aperture and the second substrate. One or more vias are provided to access I/O signals at a surface of the first or second substrates. The modules may include an invariant die where different technologies are stacked together.

What is claimed is: 
     
         1 . A wafer structure comprising:
 a first planar structure having a plurality of apertures defined therein;   at least one module positioned with respect to one of the apertures, the at least one module having a plurality of beam leads coupled to the first planar structure; and   a second planar structure disposed on a first surface of the first planar structure to define a closed space about the at least one module,   wherein the at least one module comprises:
 a first circuit layer; and 
 a second circuit layer coupled to the first circuit layer, 
 wherein at least one of the first and second circuit layers is coupled to at least one of the plurality of beam leads. 
   
     
     
         2 . The wafer structure of  claim 1 , wherein:
 the first circuit layer is manufactured by a first type of manufacturing process; and   the second circuit layer is manufactured by a second type of manufacturing process different from the first type of manufacturing process.   
     
     
         3 . The wafer structure of  claim 1 , wherein the closed space is hermetically sealed. 
     
     
         4 . The wafer structure of  claim 1 , wherein the at least one module comprises:
 a lid; and   at least one mode suppression circuit disposed in the lid.   
     
     
         5 . The wafer structure of  claim 4 , wherein the at least one mode suppression circuit comprises a plurality of active elements configured to form an active electronic band gap circuit. 
     
     
         6 . The wafer structure of  claim 5 , wherein the suppression circuit further comprises at least one resistor and at least one transistor,
 whereby the at least one mode suppression circuit provides dynamic mode suppression.   
     
     
         7 . The wafer structure of  claim 4 , wherein the at least one mode suppression circuit comprises:
 a plurality of passive elements configured to form a passive electronic band gap surface; and   at least one cavity,   whereby the at least one mode suppression circuit provides passive mode suppression.   
     
     
         8 . The wafer structure of  claim 7 , wherein each passive element comprises:
 a cell structure comprising:
 a top layer comprising an electrically conductive pad; 
 a middle layer comprising a plurality of electrically resistive pads; 
 a lower layer comprising electrically conductive material; and 
 a via electrically coupling the top layer electrically conductive pad to the lower layer electrically conductive material. 
   
     
     
         9 . The wafer structure of  claim 8 , wherein each electrically conductive pad comprises Au. 
     
     
         10 . The wafer structure of  claim 8 , wherein each electrically resistive pad comprises NiCr. 
     
     
         11 . The wafer structure of  claim 8 , wherein the electrically conductive material comprises Au. 
     
     
         12 . The wafer structure of  claim 1 , further comprising:
 a suspended stripline structure coupling the at least one of the first and second circuit layers to the at least one of the plurality of beam leads.   
     
     
         13 . The wafer structure of  claim 12 , wherein the suspended stripline structure comprises:
 a first conductive layer;   a second conductive layer spaced apart from the first conductive layer; and   a plurality of vias electrically coupling the first conductive layer to the second conductive layer.   
     
     
         14 . The wafer structure of  claim 13 , wherein the suspended stripline structure further comprises:
 an air space disposed between the first and second conductive layers.   
     
     
         15 . The wafer structure of  claim 13 , wherein the suspended stripline structure further comprises:
 a first conductive trace provided on the first conductive layer; and   a second conductive trace provided on the second conductive layer,   wherein the plurality of vias electrically couple the first conductive trace to the second conductive trace.   
     
     
         16 . The wafer structure of  claim 13 , wherein the suspended stripline structure further comprises:
 a cover layer defining a first cavity disposed adjacent the first conductive layer; and   a base layer defining a second cavity disposed adjacent the second conductive layer.   
     
     
         17 . The wafer structure of  claim 16 , wherein each of the cover and base layers comprises a low-loss dielectric material. 
     
     
         18 . The wafer structure of  claim 16 , wherein the first and second cavities are longitudinally aligned with one another. 
     
     
         19 . The wafer structure of  claim 18 , wherein the plurality of vias are arranged in alignment with the first and second cavities. 
     
     
         20 . A device, comprising:
 a first planar structure having a first surface;   a first aperture defined in the first surface of the first planar structure;   a first module having a plurality of co-planar leads extending therefrom, wherein the plurality of co-planar leads is coupled to the first surface of the first planar structure to position the first module in the first aperture;   a second planar structure disposed on the first surface of the first planar structure,   wherein a closed space is defined about the first module by the first and second planar structures and the first aperture.   
     
     
         21 . The device of  claim 20 , further comprising:
 at least one signal path trace disposed on the first planar structure,   wherein at least one of the co-planar leads is coupled to the at least one signal path trace.   
     
     
         22 . The device of  claim 20 , further comprising:
 a first signal path trace disposed on the first planar structure;   a second signal path trace disposed on the second planar structure; and   a via disposed in the second planar structure, the via coupled to the second signal path trace,   wherein the via is coupled to a node on the first signal path trace, and   wherein at least one of the co-planar leads is coupled to the at least one signal path trace.   
     
     
         23 . The device of  claim 22 , wherein the closed space is hermetically sealed. 
     
     
         24 . The device of  claim 20 , wherein the first module comprises:
 a lid; and   at least one mode suppression circuit disposed in the lid.   
     
     
         25 . The device of  claim 24 , wherein the at least one mode suppression circuit comprises a plurality of active elements configured to form an active electronic band gap circuit. 
     
     
         26 . The device of  claim 25 , wherein the suppression circuit further comprises at least one resistor and at least one transistor,
 whereby the at least one mode suppression circuit provides dynamic mode suppression.   
     
     
         27 . The device of  claim 24 , wherein the at least one mode suppression circuit comprises:
 a plurality of passive elements configured to form a passive electronic band gap surface; and   at least one cavity,   whereby the at least one mode suppression circuit provides passive mode suppression.   
     
     
         28 . The device of  claim 27 , wherein each passive element comprises:
 a cell structure comprising:
 a top layer comprising an electrically conductive pad; 
 a middle layer comprising a plurality of electrically resistive pads; 
 a lower layer comprising electrically conductive material; and 
 a via electrically coupling the top layer electrically conductive pad to the lower layer electrically conductive material. 
   
     
     
         29 . The device of  claim 28 , wherein each electrically conductive pad comprises Au. 
     
     
         30 . The device of  claim 28 , wherein each electrically resistive pad comprises NiCr. 
     
     
         31 . The device of  claim 28 , wherein the electrically conductive material comprises Au. 
     
     
         32 . The device of  claim 20 , wherein the first module comprises:
 a first circuit layer; and   a second circuit layer coupled to the first circuit layer,   wherein at least one of the first and second circuit layers is coupled to at least one of the co-planar leads.   
     
     
         33 . The device of  claim 32 , wherein the first and second circuit layers are electrically and mechanically coupled to one another. 
     
     
         34 . The device of  claim 32 , wherein at least one of the first and second circuit layers is electrically coupled to at least one of the co-planar leads. 
     
     
         35 . The device of  claim 32 , wherein:
 the first circuit layer is manufactured by a first type of manufacturing process; and   the second circuit layer is manufactured by a second type of manufacturing process different from the first type of manufacturing process.   
     
     
         36 . The device of  claim 32 , further comprising:
 a suspended stripline structure coupling the at least one of the first and second circuit layers to the at least one of the plurality of beam leads.   
     
     
         37 . The device of  claim 36 , wherein the suspended stripline structure comprises:
 a first conductive layer;   a second conductive layer spaced apart from the first conductive layer; and   a plurality of vias electrically coupling the first conductive layer to the second conductive layer.   
     
     
         38 . The device of  claim 37 , wherein the suspended stripline structure further comprises:
 an air space disposed between the first and second conductive layers.   
     
     
         39 . The device of  claim 37 , wherein the suspended stripline structure further comprises:
 a first conductive trace provided on the first conductive layer; and   a second conductive trace provided on the second conductive layer,   wherein the plurality of vias electrically couple the first conductive trace to the second conductive trace.   
     
     
         40 . The device of  claim 37 , wherein the suspended stripline structure further comprises:
 a cover layer defining a first cavity disposed adjacent the first conductive layer; and   a base layer defining a second cavity disposed adjacent the second conductive layer.   
     
     
         41 . The device of  claim 40 , wherein each of the cover and base layers comprises a low-loss dielectric material. 
     
     
         42 . The device of  claim 40 , wherein the first and second cavities are longitudinally aligned with one another. 
     
     
         43 . The device of  claim 42 , wherein the plurality of vias are arranged in alignment with the first and second cavities.