Capacitive mismatch measurement

Abstract

An analog-to-digital converter (ADC) comprising successive approximation circuitry, a capacitive analog-to-digital converter (CDAC), and capacitor mismatch measurement circuitry. The successive approximation circuitry is configured to control conversion of an analog signal to a digital value. The CDAC is coupled to the successive approximation circuitry. The CDAC includes a plurality of capacitors. The capacitor mismatch measurement circuitry is coupled to the CDAC. The capacitor mismatch measurement circuitry includes a first oscillator circuit, a second oscillator circuit, and counter circuitry. The first oscillator circuit is configured to oscillate at a frequency determined by a capacitance of one of the capacitors. The second oscillator circuit is configured to generate a predetermined time interval. The counter circuitry is configured to count a number of cycles of oscillation of the first oscillator in the predetermined time interval.

What is claimed is: 
     
         1 . A system for measuring capacitive mismatch, comprising:
 a plurality of capacitors;   a first oscillator circuit configured to oscillate at a frequency determined by a capacitance of one of the capacitors; and   a second oscillator circuit configured to generate a predetermined time interval; and   counter circuitry configured to count a number of cycles of oscillation of the first oscillator in the predetermined time interval.   
     
     
         2 . The system of  claim 1 , wherein the first oscillator circuit comprises:
 a comparator;   a plurality of switches, each of the switches configured to connect one of the capacitors to the comparator; and   a current source configured to generate a current to charge the one of the capacitors connected to the comparator.   
     
     
         3 . The system of  claim 2 , further comprising control circuitry configured to control the plurality of switches to individually connect each of the capacitors to the comparator. 
     
     
         4 . The system of  claim 3 , wherein the control circuitry is configured to control the plurality of switches to connected each of the capacitors to the comparator in parallel with a different one of the capacitors. 
     
     
         5 . The system of  claim 1 , wherein the second oscillator comprises:
 a comparator;   a capacitor; and   a current source configured to generate a current to charge the capacitor connected to the comparator.   
     
     
         6 . The system of  claim 1 , wherein the counter circuitry comprises:
 a first counter configured to generate the predetermined time interval as a predetermined number of cycles of oscillation of the second oscillator; and   a second counter configured to count the number of cycles of oscillation of the first oscillator in the predetermined time interval.   
     
     
         7 . The system of  claim 1 , further comprising communication circuitry configured to transmit the count of the number of cycles of oscillation of the first oscillator in the predetermined time interval to a device external to the system. 
     
     
         8 . A method for measuring capacitor mismatch, comprising:
 switching a first capacitor into a first relaxation oscillator;   generating a clock signal output at a first frequency by the first relaxation oscillator;   generating a clock signal output by a second relaxation oscillator;   counting a predetermined number of cycles of the clock signal output by the second relaxation oscillator to generate a measurement interval;   counting a number of cycles of the clock signal output by the first relaxation oscillator in the measurement interval; and   determining a difference between the first capacitor and a different capacitor based on the number of cycles of the clock signal output by the first relaxation oscillator in the measurement interval.