Efficient data transfer between a processor core and an accelerator

Abstract

A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

What is claimed is: 
     
         1 . A computing device comprising:
 means for writing input data to a first cache line of a cache shared with an accelerator, wherein the input data is ready to be operated on by the accelerator;   means for writing instructions to one or more cache lines, the one or more cache lines designated as a queue for the accelerator, wherein the instructions indicate a first operation to be performed by the accelerator and a virtual pointer to the input data in the cache;   means for determining that output data of the accelerator is ready to be consumed, the output data being located at the first cache line or at an additional cache line of the cache, wherein the first cache line or the additional cache line comprises a set first flag that indicates the first cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the first cache line or the additional cache line until the output data is read;   means for reading and processing the output data from the first cache line or the additional cache line; and   means for removing the first flag from the cache line or the additional cache line responsive to the output data being processed.   
     
     
         2 . The computing device of  claim 1 , further comprising means for setting a second flag in the first cache line or the additional cache line responsive to the output data, wherein the second flag marks the first cache line or the additional cache line as being least recently used. 
     
     
         3 . The computing device of  claim 1 , further comprising means for setting a second flag in the first cache line responsive to the accelerator accessing the input data in the first cache line. 
     
     
         4 . The computing device of  claim 1 , wherein the cache comprises a last level cache. 
     
     
         5 . The computing device of  claim 1 , further comprising:
 means for reading the input data in the first cache line of the cache by the accelerator;   means for marking the input data in the first cache line as least recently used by the accelerator;   means for performing a second operation on the input data by the accelerator to generate the output data; and   means for writing the output data into the first cache line or the additional cache line.   
     
     
         6 . The computing device of  claim 1 , further comprising means for changing a state of the first cache line from modified to exclusive by the accelerator. 
     
     
         7 . The computing device of  claim 1 , further comprising:
 means for performing a second operation on a particular cache line that is monitored by a monitor logic associated with the accelerator, wherein the monitor logic is to:
 detect that the means for performing has performed the second operation on the particular cache line; and 
 notify the accelerator that the input data on the particular cache line is ready to be operated on by the accelerator responsive to detecting that the second operation has been performed. 
   
     
     
         8 . The computing device of  claim 7 , wherein the second operation comprises a read invalidate own operation, and wherein the monitor logic is to wake the accelerator responsive to detecting the read invalidate own operation on the particular cache line. 
     
     
         9 . The computing device of  claim 1 , wherein the means for determining that the output data of the accelerator is ready to be consumed comprises:
 means for monitoring the accelerator performing a second operation on a particular cache line;   means for detecting that the accelerator has performed the second operation on the particular cache line; and   means for notifying that the output data is ready to be consumed responsive to the second operation on the particular cache line being performed.   
     
     
         10 . The computing device of  claim 9 , wherein the second operation comprises a read invalidate own operation on the particular cache line by the accelerator. 
     
     
         11 . An apparatus comprising:
 a cache;   an accelerator coupled to the cache; and   a processor coupled to the accelerator and the cache, wherein the processor comprises:
 means for writing input data to a first cache line of the cache, wherein the input data is ready to be operated on by the accelerator; and 
 means for writing instructions to one or more cache lines, the one or more cache lines designated as a queue for the accelerator, wherein the instructions indicate a first operation to be performed by the accelerator and a virtual pointer to the input data in the cache. 
   
     
     
         12 . The apparatus of  claim 11 , wherein the processor further comprises:
 means for determining that output data of the accelerator is ready to be consumed, the output data being located at the first cache line, wherein the first cache line comprises a set first flag that indicates the first cache line was modified by the accelerator and that prevents the output data from being removed from the first cache line until the output data is read by the processor;   means for reading and processing the output data from the first cache line;   means for removing the first flag from the first cache line; and   means for setting a second flag in the first cache line, wherein the second flag marks the first cache line as being least recently used.   
     
     
         13 . The apparatus of  claim 12 , wherein the processor further comprises:
 means for determining that output data of the accelerator is ready to be consumed, the output data being located at the first cache line, wherein the first cache line comprises a set first flag that indicates the first cache line was modified by the accelerator and that prevents the output data from being removed from the first cache line until the output data is read by the processor;   means for reading and processing the output data from the first cache line;   means for removing the first flag from the first cache line; and   means for setting a second flag in the first cache line responsive to the accelerator accessing the input data in the first cache line.   
     
     
         14 . The apparatus of  claim 11 , wherein the processor further comprises:
 means for determining that output data of the accelerator is ready to be consumed, the output data being located at a second cache line of the cache, wherein the second cache line comprises a set first flag that indicates the second cache line was modified by the accelerator and that prevents the output data from being removed from the second cache line until the output data is read by the processor;   means for reading and processing the output data from the second cache line;   means for removing the first flag from the second cache line; and   means for setting a second flag in the second cache line, wherein the second flag marks the second cache line as being least recently used.   
     
     
         15 . The apparatus of  claim 14 , wherein the processor further comprises:
 a core or a thread;   means for detecting that the accelerator has performed a second operation on the second cache line; and   means for notifying the core or the thread that the output data is ready to be consumed responsive to the detecting.   
     
     
         16 . The apparatus of  claim 15 , wherein the second operation comprises a read invalidate own operation on the second cache line by the accelerator. 
     
     
         17 . The apparatus of  claim 11 , wherein the accelerator further comprises:
 means for reading the input data in the first cache line of the cache;   means for marking the input data in the first cache line as least recently used;   means for performing a second operation on the input data to generate output data; and   means for writing the output data into the first cache line or a second cache line of the cache.   
     
     
         18 . The apparatus of  claim 17 , wherein the accelerator further comprises means for changing a state of the first cache line from modified to exclusive. 
     
     
         19 . The apparatus of  claim 11 , wherein the accelerator further comprises:
 means for monitoring a second cache line;   means for performing a second operation on the second cache line;   means for detecting that a core of the processor has performed the second operation on the second cache line; and   means for notifying that the input data on the second cache line is ready to be operated on by the accelerator responsive to the second operation on the second cache line being detected.   
     
     
         20 . The apparatus of  claim 19 , wherein the second operation comprises a read invalidate own operation, and wherein the apparatus further comprises means for waking the accelerator responsive to the read invalidate own operation on the second cache line being detected.