MIDDLE-OF-LINE (MOL) METAL RESISTOR TEMPERATURE SENSORS FOR LOCALIZED TEMPERATURE SENSING OF ACTIVE SEMICONDUCTOR AREAS IN INTEGRATED CIRCUITS (ICs)

Abstract

Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

What is claimed is: 
     
         1 . A method of sensing temperature in a semiconductor die for an integrated circuit (IC), comprising:
 forming a substrate;   forming an active semiconductor layer above the substrate;   forming at least one semiconductor device in the active semiconductor layer;   forming a middle-of-line (MOL) layer above the active semiconductor layer, comprising:
 forming a metal resistor having a resistance and comprising a first metal material in the MOL layer, the metal resistor comprising a first contact area and a second contact area and having a resistance between the first contact area and the second contact area; 
   forming a first contact above the metal resistor in the MOL layer and in contact with the first contact area of the metal resistor;   forming a second contact above the metal resistor in the MOL layer and in contact with the second contact area of the metal resistor;   forming at least one interconnect layer above the MOL layer;   forming a first interconnect in the at least one interconnect layer electrically coupled to the first contact, to electrically couple the first interconnect to the first contact area of the metal resistor; and   forming a second interconnect in the at least one interconnect layer electrically coupled to the second contact, to electrically couple the second interconnect to the second contact area of the metal resistor.   
     
     
         2 . The method of  claim 1 , wherein the resistance of the metal resistor is a function of an ambient temperature of the metal resistor. 
     
     
         3 . The method of  claim 1 , wherein forming the MOL layer comprises forming the MOL layer of a thickness of approximately eighteen (18) nanometers (nm) or less above the active semiconductor layer. 
     
     
         4 . The method of  claim 1 , wherein:
 forming the at least one semiconductor device in the active semiconductor layer comprises forming a transistor in the active semiconductor layer comprising a source, a drain, and a gate interdisposed between the source and the drain; and   forming the metal resistor comprises forming the metal resistor having the resistance comprising the first metal material in the MOL layer adjacent to the gate of the transistor to be exposed to an ambient temperature of the gate of the transistor.   
     
     
         5 . The method of  claim 4 , wherein:
 the gate comprises:
 a dielectric layer comprising a dielectric material; 
 a conductive layer comprising a conductive material; 
 a work function layer comprising a work function material disposed between the dielectric material and the conductive material; and 
   the first metal material comprises the work function material.   
     
     
         6 . The method of  claim 1 , further comprising:
 forming a first vertical interconnect access (via) the first interconnect, the first via in contact with the first contact area of the metal resistor and the first interconnect, to electrically couple the first contact area to the first interconnect; and   forming a second via disposed in the second interconnect, the second via in contact with the second contact area of the metal resistor and the second interconnect, to electrically couple the second contact area to the second interconnect.   
     
     
         7 . The method of  claim 1 , wherein forming the MOL layer above the active semiconductor layer, comprises:
 forming a first dielectric layer comprising a first dielectric material above the active semiconductor layer;   forming a metal layer comprising the first metal material above the first dielectric layer;   forming a second dielectric layer comprising a second dielectric material above the metal layer;   disposing a hard mask above a first portion of the second dielectric layer; and   removing a second portion of the metal layer and the second dielectric layer outside of the first portion down to the first dielectric layer to leave a remaining portion of the metal layer and a remaining portion of the second dielectric layer below the hard mask, the remaining portion forming the metal resistor having the resistance.   
     
     
         8 . An integrated circuit (IC), comprising:
 an active semiconductor layer;   a middle-of-line (MOL) layer disposed above the active semiconductor layer;   a MOL temperature sensor comprising a metal resistor disposed in the MOL layer, the metal resistor having a resistance that changes as a function of a change in an ambient temperature of the metal resistor;   a voltage source electrically coupled to the metal resistor, the voltage source configured to apply a first voltage to the metal resistor;   a voltage detector circuit configured to sense a second voltage as a function of the ambient temperature of the metal resistor when the first voltage is applied to the metal resistor; and   a measurement circuit configured to measure the ambient temperature of the metal resistor based on a voltage level of the second voltage, and generate a temperature signal on an output node representing an ambient temperature value of the metal resistor.   
     
     
         9 . The IC of  claim 8 , further comprising a semiconductor device disposed in the active semiconductor layer;
 wherein:
 the metal resistor is disposed in the MOL layer adjacent to the semiconductor device to be exposed to an ambient temperature of the semiconductor device; and 
 the measurement circuit is configured to measure the ambient temperature of the metal resistor based on the voltage level of the sensed second voltage, to measure the ambient temperature of the semiconductor device. 
   
     
     
         10 . The IC of  claim 9 , wherein:
 the semiconductor device comprises a transistor comprising a source, a drain, and a gate interdisposed between the source and the drain;   the metal resistor is disposed in the MOL layer adjacent to the gate of the transistor to be exposed to an ambient temperature of the gate of the transistor; and   the measurement circuit is configured to measure the ambient temperature of the metal resistor based on the voltage level of the sensed second voltage, to measure the ambient temperature of the gate of the transistor.   
     
     
         11 . The IC of  claim 8 , wherein the voltage detector circuit comprises a voltage divider circuit comprising a reference resistor coupled between the output node and a reference node, and the metal resistor coupled to the output node;
 the voltage divider circuit configured to divide the first voltage applied to the metal resistor between the metal resistor and the reference resistor to generate an output voltage as the second voltage; and   the measurement circuit configured to measure the ambient temperature of the metal resistor based on a voltage level of the output voltage.   
     
     
         12 . The IC of  claim 8 , wherein the measurement circuit comprises an analog-to-digital (A/D) circuit configured to generate the ambient temperature value by converting the second voltage into a digital temperature value.