Semiconductor memory devices

Abstract

A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

1 .- 9 . (canceled) 
     
     
         10 . A method for manufacturing a semiconductor memory device, comprising:
 forming a stacking structure by alternately stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate;   forming a channel hole by penetrating the plurality of insulating layers and the plurality of sacrificial layers;   forming a lower semiconductor layer on the substrate exposed by the channel hole, the lower semiconductor layer having an upper surface inclined such that a first portion of the upper surface of the lower semiconductor layer is lower than a second portion of the upper surface of the lower semiconductor layer;   forming a vertical insulating pattern on an inner wall of the channel hole; and   forming a vertical channel pattern on an inner surface of the vertical insulating pattern and contacting the lower semiconductor layer in the channel hole,   wherein a first level of a bottom of the vertical channel pattern is lower than a second level of the first portion of the upper surface of the lower semiconductor layer.   
     
     
         11 . The method for manufacturing a semiconductor memory device of  claim 10 , wherein the forming of the vertical insulating pattern includes:
 forming a vertical insulating layer on the inner wall of the channel hole and on a top of the lower semiconductor layer; and   anisotropically etching the vertical insulating layer on the top of the lower semiconductor layer such that the lower semiconductor layer includes a recess region recessed concavely toward the substrate, and   wherein the first portion of the upper surface of the lower semiconductor layer is closest to the substrate.   
     
     
         12 . The method for manufacturing a semiconductor memory device of  claim 11 , further comprising:
 forming a sacrificial channel layer in the channel hole;   anisotropically etching the sacrificial channel layer with the vertical insulating layer; and   removing the sacrificial channel layer.   
     
     
         13 . The method for manufacturing a semiconductor memory device of  claim 12 , further comprising partially etching the lower semiconductor layer that overlaps with the sacrificial channel layer. 
     
     
         14 . The method for manufacturing a semiconductor memory device of  claim 11 , wherein an outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor layer along a curve of the recess region. 
     
     
         15 . The method for manufacturing a semiconductor memory device of  claim 10 , wherein the vertical insulating pattern comprises:
 a tunnel insulating layer contacting a surface of the vertical channel pattern;   a charge storing layer positioned between the tunnel insulating layer and the stacking structure; and   a blocking insulating layer positioned between the charge storing layer and the stacking structure, and   wherein each of the tunnel insulating layer, the charge storing layer, and the blocking insulating layer comprises a vertical part that extends in a vertical direction to the substrate, and   wherein each of the blocking insulating layer and the charge storing layer comprises a protrusion that is connected with the vertical part thereof and extends on the lower semiconductor layer.   
     
     
         16 . The method for manufacturing a semiconductor memory device of  claim 10 , wherein after the forming of the vertical insulating pattern, a lower part of the channel hole has a first width above a lowest contact point in which the channel hole contacts the vertical insulating pattern, and a second width below the lowest contact point, and
 wherein the first width is equal to or greater than the second width.   
     
     
         17 . The method for manufacturing a semiconductor memory device of  claim 10 , further comprising forming a first region doped with a first impurity within the lower semiconductor layer through an ion injection process after the forming of the lower semiconductor layer. 
     
     
         18 . The method for manufacturing a semiconductor memory device of  claim 10 , wherein an upper part of the vertical channel pattern contacting the vertical insulating pattern has a first thickness,
 wherein a lower part of the vertical channel pattern contacting the lower semiconductor layer has a second thickness, and   wherein the second thickness is substantially equal to the first thickness.   
     
     
         19 . A method for manufacturing a semiconductor memory device, comprising:
 forming a stacking structure by alternately stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate;   forming a channel hole by penetrating the plurality of insulating layers and the plurality of sacrificial layers;   forming a lower semiconductor layer on the substrate exposed by the channel hole;   forming a vertical insulating pattern on an inner wall of the channel hole; and   forming a vertical channel pattern on an inner surface of the vertical insulating pattern and contacting the lower semiconductor layer in the channel hole,   wherein an upper surface of the lower semiconductor layer is inclined such that a first portion of the upper surface of the lower semiconductor layer is lower than a second portion of the upper surface of the lower semiconductor layer, and   a first level of an upper surface of a lower part of the vertical channel pattern contacting the lower semiconductor layer is lower than a second level of the second portion of the upper surface of the lower semiconductor layer.   
     
     
         20 . The method of  claim 19 , wherein the first portion of the upper surface of the lower semiconductor layer is closest to the substrate. 
     
     
         21 . The method of  claim 20 , wherein a third level of a bottom of the vertical channel pattern is lower than a fourth level of the first portion of the upper surface of the lower semiconductor layer. 
     
     
         22 . The method for manufacturing a semiconductor memory device of  claim 20 , wherein after the forming of the vertical insulating pattern, a lower part of the channel hole has a first width above a lowest contact point in which the channel hole contacts the vertical insulating pattern, and a second width below the lowest contact point, and
 wherein the first width is equal to or greater than the second width.   
     
     
         23 . A method for manufacturing a semiconductor memory device, comprising:
 forming a stacking structure by alternately stacking a plurality of insulating layers and a plurality of sacrificial layers on a substrate;   forming a channel hole by penetrating the plurality of insulating layers and the plurality of sacrificial layers;   forming a lower semiconductor layer on the substrate exposed by the channel hole;   forming a first region doped with a first impurity within the lower semiconductor layer through an ion injection process;   forming a vertical insulating pattern on an inner wall of the channel hole; and   forming a vertical channel pattern on an inner surface of the vertical insulating pattern and contacting the lower semiconductor layer in the channel hole.   
     
     
         24 . The method for manufacturing a semiconductor device of  claim 23 , further comprising forming a second region doped with a second impurity, different from the first impurity, within the lower semiconductor layer. 
     
     
         25 . The method for manufacturing a semiconductor device of  claim 24 , wherein the first region comprises a largest content of the first impurity among a plurality of regions of the lower semiconductor layer that are doped with the first impurity, and the second region comprises a largest content of the second impurity among a plurality of regions of the lower semiconductor layer that are doped with the second impurity, and
 a first width of the first region is different from a second width of the second region.   
     
     
         26 . The method for manufacturing a semiconductor device of  claim 23 , wherein an upper surface of the lower semiconductor layer is inclined such that a first portion of the upper surface of the lower semiconductor layer is lower than a second portion of the upper surface of the lower semiconductor layer, and
 a first level of an upper surface of a lower part of the vertical channel pattern contacting the lower semiconductor layer is lower than a second level of the first portion of the upper surface of the lower semiconductor layer.   
     
     
         27 . The method for manufacturing a semiconductor device of  claim 23 , wherein the forming of the first region is performed after the forming of the lower semiconductor layer. 
     
     
         28 . The method for manufacturing a semiconductor device of  claim 23 , wherein the forming of the first region is performed before the forming of the vertical channel pattern. 
     
     
         29 . The method for manufacturing a semiconductor device of  claim 23 , wherein the lower semiconductor layer has an upper surface inclined such that a first portion of the upper surface of the lower semiconductor layer is lower than a second portion of the upper surface of the lower semiconductor layer, and
 a first level of a bottom of the vertical channel pattern is lower than a second level of the first portion of the upper surface of the lower semiconductor layer.