Programmable logic device with integrated network-on-chip

Abstract

Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

What is claimed is: 
     
         1 . An integrated circuit system, comprising:
 a programmable logic circuitry;   an array of programmable hardened circuitry stations configurable to receive data from or send the data to the programmable logic circuitry, wherein the array of programmable hardened circuitry stations comprises:
 a first hardened circuitry station; 
 a second hardened circuitry station; 
 a third hardened circuitry station; 
 a first direct communication path between the first hardened circuitry station and the second hardened circuitry station; and 
 a second direct communication path between the second hardened circuitry station and the third hardened circuitry station; 
   wherein the first hardened circuitry station is configurable to route the data to the third hardened circuitry station through the second hardened circuitry station, wherein the third hardened circuitry station is configurable to process the data, and wherein the second hardened circuitry station is configurable not to process the data   
     
     
         2 . The integrated circuit system of  claim 1 , wherein the third hardened circuitry station is configurable to send the data to the programmable logic circuitry. 
     
     
         3 . The integrated circuit system of  claim 1 , wherein the array of programmable hardened circuitry stations communicates data to or from the programmable logic circuitry in a bi-directional manner. 
     
     
         4 . The integrated circuit system of  claim 1 , wherein the array of programmable hardened circuitry stations is clocked at a different rate than the programmable logic circuitry. 
     
     
         5 . The integrated circuit system of  claim 1 , wherein the array of programmable hardened circuitry stations is communicatively coupled to the programmable logic circuitry via multiple nodes, wherein the array of programmable hardened circuitry stations comprises an array of programmable hardened intellectual property (IP) stations. 
     
     
         6 . The integrated circuit system of  claim 1 , wherein the array of programmable hardened circuitry stations is clocked at a higher rate than the programmable logic circuitry. 
     
     
         7 . The integrated circuit system of  claim 1 , wherein the array of programmable hardened circuitry stations is programmable to perform signal processing on data received from the programmable logic circuitry. 
     
     
         8 . The integrated circuit system of  claim 1 , comprising a plurality of interconnections that route data between programmable hardened circuitry stations of the array of programmable hardened circuitry stations. 
     
     
         9 . The integrated circuit system of  claim 8 , wherein the plurality of interconnections communicatively connect the first programmable hardened circuitry station to the second programmable hardened circuitry station in a unidirectional manner. 
     
     
         10 . The integrated circuit system of  claim 8 , wherein the plurality of interconnections are configurable based on software-generated code. 
     
     
         11 . The integrated circuit system of  claim 1 , wherein the array of programmable hardened circuitry stations is communicatively coupled to distributed memory, wherein each programmable hardened circuitry station of the array of programmable hardened circuitry stations is associated with at least one memory block of the distributed memory. 
     
     
         12 . An integrated circuit system, comprising:
 programmable logic circuitry;   a memory interface configurable to communicatively couple to a double data rate (DDR) memory;   input/output (I/O) circuitry; and   a network-on-chip (NOC) comprising one or more clock-crossing buffers associated with a plurality of network-on-chip (NOC) nodes, wherein the NOC substantially spans a north-south height and east-west width of the integrated circuit system, and wherein the NOC is configurable to communicatively couple the programmable logic circuitry, the I/O circuitry, and the memory interface in a packetized and bi-directional manner.   
     
     
         13 . The integrated circuit system of  claim 12 , wherein the NOC comprises vertical NOC columns configurable to connect between logic regions of the programmable logic circuitry. 
     
     
         14 . The integrated circuit system of  claim 12 , wherein the one or more clock-crossing buffers facilitates communication between the NOC and the programmable logic circuitry by buffering communication between a first clock rate of the NOC and a second clock rate of the programmable logic circuitry. 
     
     
         15 . The integrated circuit system of  claim 12 , wherein the NOC is communicatively coupled to the programmable logic circuitry via one or more NOC nodes. 
     
     
         16 . The integrated circuit system of  claim 12 , wherein the NOC communicates data to the programmable logic circuitry and the I/O circuitry in a unidirectional manner. 
     
     
         17 . The integrated circuit system of  claim 12 , wherein the NOC is in a separate region of the integrated circuit system than the programmable logic circuitry. 
     
     
         18 . The integrated circuit system of  claim 12 , wherein the NOC is addressable. 
     
     
         19 . A method for operating an integrated circuit system comprising:
 configuring field-programmable gate array (FPGA) programmable logic circuitry;   processing data using a first plurality of hardened circuitry nodes; and   communicating data from the FPGA programmable logic circuitry to at least one hardened circuitry node of the first plurality of hardened circuitry nodes via a second plurality of hardened circuitry nodes configurable to operate as bi-directional NOC nodes, wherein the second plurality of hardened circuitry nodes do not process the data.   
     
     
         20 . The method of  claim 19 , wherein communicating the data from the FPGA programmable logic circuitry to the at least one hardened circuitry node comprises transferring the data in a packetized manner.