Screen printing electrical contacts to nanostructured areas

Abstract

A process is provided for contacting a nanostructured surface. The process may include (a) providing a substrate having a nanostructured material on a surface, (b) passivating the surface on which the nanostructured material is located, (c) screen printing onto the nanostructured surface and (d) firing the screen printing ink at a high temperature. In some embodiments, the nanostructured material compromises silicon. In some embodiments, the nanostructured material includes silicon nanowires. In some embodiments, the nanowires are around 150 nm, 250 nm, or 400 nm in length. In some embodiments, the nanowires have a diameter range between about 30 nm and about 200 nm. In some embodiments, the nanowires are tapered such that the base is larger than the tip. In some embodiments, the nanowires are tapered at an angle of about 1 degree, about 3 degrees, or about 10 degrees. In some embodiments, a high temperature can be approximately 700 C, 750 C, 800 C, or 850 C.

What is claimed is: 
     
         1 . A silicon nanostructured device comprising:
 a non-nanostructured polycrystalline silicon substrate;   a nanostructured area disposed on and contacting a surface of the substrate;   a first contact comprising a comb-like pattern of metal directly electrically contacting the nanostructured area;   a p-n junction below the nanostructured area; and   a second metal contact in electrical contact with the substrate.   
     
     
         2 . The device of  claim 1 , suitable for use as a solar cell. 
     
     
         3 . The device of  claim 1 , wherein the nanostructures are made from p-type silicon. 
     
     
         4 . The device of  claim 1 , wherein the nanostructures are made from n-type silicon. 
     
     
         5 . The device of  claim 1 , wherein lengths of nanostructures in the nanostructured area are between about 150 nm and about 400 nm. 
     
     
         6 . The device of  claim 4 , wherein nanostructures in the nanostructured area have cross-sectional diameters between about 30 nm and about 200 nm. 
     
     
         7 . The device of  claim 1 , wherein one third to one half of a volume of the nanostructured area is silicon. 
     
     
         8 . The device of  claim 1 , wherein nanostructures in the nanostructured areas are tapered such that bases of the nanostructures on average have larger diameters than tips of the nanostructures. 
     
     
         9 . The device of  claim 1 , wherein one of the first contact or the second contact comprises silver. 
     
     
         10 . The device of  claim 9 , wherein the second metal contact comprises aluminum. 
     
     
         11 . A silicon nanostructured device comprising:
 a non-nanostructured polycrystalline silicon substrate;   a nanostructured area disposed on and contacting a surface of the substrate;   a passivating layer coating the nanostructured area, the passivating layer comprising one of aluminum oxide, silicon dioxide, or silicon nitride;   a first contact comprising a comb-like pattern of metal directly electrically contacting the nanostructured area;   a p-n junction below the nanostructured area; and   a second contact in electrical contact with the substrate.   
     
     
         12 . The device of  claim 11 , wherein at least one of the first contact or the second contact is fired at high temperature. 
     
     
         13 . The device of  claim 12 , wherein the high temperature is in a range of about 700° C. to about 900° C. 
     
     
         14 . The device of  claim 13 , wherein the high temperature is in a range of about 775° C. to about 825° C. 
     
     
         15 . The device of  claim 12 , wherein the device is heat dried before firing at high temperature. 
     
     
         16 . The device of  claim 15 , wherein the device is heat dried at a temperature in a range of about 100° C. to about 200° C. before firing at high temperature. 
     
     
         17 . The device of  claim 11 , wherein the non-nanostructured substrate comprises n-type silicon. 
     
     
         18 . The device of  claim 11 , wherein the non-nanostructured substrate comprises p-type silicon.