Simulation system estimating self-heating characteristic of circuit and design method thereof

Abstract

A method of designing a semiconductor circuit using a circuit simulation tool executed by a computer includes calculating power consumptions of elements of the semiconductor circuit by use of the circuit simulation tool. A thermal netlist is created about the semiconductor circuit, based on the power consumptions and geometry information of each of the elements. A simulation of the semiconductor circuit is performed with the thermal netlist using the circuit simulation tool to detect a temperature of each of the elements. The thermal netlist includes thermal capacitance information of each of the elements.

What is claimed is: 
     
         1 . A method of designing a semiconductor circuit using a schematic tool executed by a computer, the method comprising:
 applying the schematic tool to an electric netlist of the semiconductor circuit to calculate power consumptions of elements of the semiconductor circuit;   creating a thermal netlist about the semiconductor circuit based on the power consumptions and geometry information of each of the elements, by replacing an electrical resistance of each of the elements within the electric netlist with a thermal resistance or a thermal capacitance;   performing a simulation of the semiconductor circuit's operation with the thermal netlist using the schematic tool to detect a temperature variation of each of the elements during the simulated operation of the semiconductor circuit; and   modifying the semiconductor circuit, based upon the detected temperature variation of each of the elements to create a modified semiconductor circuit,   wherein the thermal netlist includes thermal capacitance information of each of the elements.   
     
     
         2 . The method of  claim 1 , further comprising receiving the electrical netlist of the semiconductor circuit. 
     
     
         3 . The method of  claim 2 , wherein in creating the thermal netlist, an electrical resistance of each of the elements of the electrical netlist is replaced with a thermal resistance and a thermal capacitance of the thermal netlist. 
     
     
         4 . The method of  claim 3 , wherein the thermal netlist includes:
 a first thermal resistance connected between source and channel nodes of a transistor;   a second thermal resistance connected between a drain node and the channel node; and   a third thermal resistance connecting a gate node and the channel node.   
     
     
         5 . The method of  claim 4 , wherein the thermal netlist further includes:
 a first thermal capacitance connected between the source node and the channel node; and   a second thermal capacitance connected between the channel node and the drain node.   
     
     
         6 . The method of  claim 5 , wherein the first thermal resistance and the first thermal capacitance are connected in parallel with each other, and wherein the second thermal resistance and the second thermal capacitance are connected in parallel with each other. 
     
     
         7 . The method of  claim 4 , wherein the thermal netlist further includes:
 an oxide film thermal resistance connected between the gate node and the channel node; and   a thermal resistance connected between the gate node and the drain node.   
     
     
         8 . The method of  claim 4 , wherein the thermal netlist further includes:
 at least one thermal resistance connected between a bulk node of the transistor and at least one of the source node, the channel node, and the drain node.   
     
     
         9 . The method of  claim 8 , wherein the thermal netlist further includes:
 a thermal resistance connecting the bulk node and a substrate node of the transistor.   
     
     
         10 . The method of  claim 3 , wherein the thermal resistance is determined based on geometry information and material characteristic information of each of the elements. 
     
     
         11 . The method of  claim 10 , wherein the thermal capacitance is determined based on a value of the thermal resistance and a time constant. 
     
     
         12 . The method of  claim 3 , wherein in creating the thermal netlist, the power consumption is provided as a power parameter of the thermal netlist. 
     
     
         13 . The method of  claim 1 , wherein in detecting the temperature, the circuit simulation tool indicates a temperature of each of the nodes with a voltage output value of each of nodes constituting a thermal circuit. 
     
     
         14 . The method of  claim 1 , further comprising:
 reconstructing the electric netlist of the semiconductor circuit depending on the detected temperature information.   
     
     
         15 . The method of  claim 14 , further comprising:
 performing simulation about the electric netlist by means of the circuit simulation tool.   
     
     
         16 . A method of designing a semiconductor circuit using a circuit simulation tool executed by an information processing device, the method comprising:
 receiving an electric netlist of the semiconductor circuit and material and geometry information of elements included in the semiconductor circuit;   conducting a first simulation of the semiconductor circuit's operation with the electric netlist using the circuit simulation tool;   creating a thermal netlist corresponding to a thermal circuit representation of the semiconductor circuit depending on at least one of power consumptions of the elements generated according to the first simulation, the material information, and the geometry information;   performing a second simulation of the semiconductor circuit's operation with the thermal netlist using the circuit simulation tool to detect temperature variations of the elements; and   revising the electric netlist based on the detected temperature variations to create a revised electric netlist,   wherein the thermal circuit includes a thermal capacitance parameter for detecting the temperature variations of the elements dynamically.   
     
     
         17 . The method of  claim 16 , wherein the electric netlist and the revised electric netlist correspond to an electrical circuit of the semiconductor circuit. 
     
     
         18 . The method of  claim 16 , wherein in creating the thermal netlist, a resistance of the electrical circuit is replaced with a thermal resistance and a thermal capacitance of the thermal circuit. 
     
     
         19 . The method of  claim 18 , wherein in creating the thermal netlist, a transistor is modeled with a source node, a channel node, a drain node, a gate node, and either at least one thermal resistance or at least one thermal capacitance connecting bulk nodes. 
     
     
         20 . The method of  claim 19 , wherein a first thermal resistance and a first thermal capacitance are connected in parallel between the channel node and the source node, and a second thermal resistance and a second thermal capacitance are connected in parallel between the channel node and the drain node.