Siliciding method

Abstract

An integrated circuit includes first semiconductor regions each having a silicided portion with group-III, group-IV, and/or group-V atoms implanted therein. In each first semiconductor region, a concentration of the group-III, group-IV, and/or group-V atoms is maximum at an interface between the silicided portion and a non-silicided portion. Other semiconductor regions in the integrated circuit each include a silicided portion also having group-III, group-IV, and/or group-V atoms implanted therein. The silicided portions of the first semiconductor regions are thicker than the silicided portions of the other semiconductor regions. The group-III, group-IV, and/or group-V atoms of the first semiconductor regions and of the other semiconductor regions may be carbon and/or germanium atoms.

1 . A method of manufacturing an integrated circuit, comprising:
 forming a first semiconductor region and a second semiconductor region within a wafer at least partially made of a semiconductor material;   performing a first siliciding of the first semiconductor region to form a first silicided region;   performing a simultaneous implantation of atoms in the first silicided region and in the second semiconductor region; and   performing a second siliciding of the second semiconductor region to form a second silicided region.   
     
     
         2 . The method of  claim 1 , wherein performing the first siliciding comprises masking the second semiconductor region followed by depositing a first metal layer on the first semiconductor region. 
     
     
         3 . The method of  claim 2 , wherein the first metal layer comprises nickel. 
     
     
         4 . The method of  claim 2 , wherein performing the second siliciding comprises depositing a second metal layer on the second semiconductor region. 
     
     
         5 . The method of  claim 4 , wherein the second metal layer comprises nickel. 
     
     
         6 . The method of  claim 4 , wherein the first metal layer is thicker than the second metal layer. 
     
     
         7 . The method of  claim 4 , wherein the second metal layer is also deposited on the first silicided region. 
     
     
         8 . The method of  claim 1 , wherein performing the first siliciding comprises performing a first annealing and wherein performing the second siliciding comprises performing a second annealing at a temperature lower than a temperature of the first annealing. 
     
     
         9 . The method of  claim 8 , wherein a duration of the second annealing is shorter than a duration of the first annealing. 
     
     
         10 . The method of  claim 1 , further comprising forming the wafer by forming a stack of a semiconductor layer, an insulating layer, and a semiconductor substrate, wherein the second semiconductor region form part of components inside and/or on top of the semiconductor layer. 
     
     
         11 . The method of  claim 10 , wherein a thickness of the semiconductor layer is smaller than 20 nm. 
     
     
         12 . The method of  claim 10 , wherein the first semiconductor region forms part of components formed inside and/or on top of the semiconductor substrate. 
     
     
         13 . The method of  claim 1 , wherein the atoms of the simultaneous implantation comprise atoms selected from the group consisting of carbon and germanium. 
     
     
         14 . The method of  claim 1 , wherein the atoms of the simultaneous implantation comprise atoms selected from the group consisting of group-III, group-IV, and group-V atoms. 
     
     
         15 . The method of  claim 1 , wherein the first and second semiconductor regions comprise silicon. 
     
     
         16 . The method of  claim 1 , wherein the simultaneous implantation is amorphizing. 
     
     
         17 . An integrated circuit, comprising:
 first semiconductor regions each comprising a silicided portion;   wherein the silicided portion includes implanted group-III, group-IV, and/or group-V atoms.   
     
     
         18 . The integrated circuit of  claim 17 , wherein the group-III, group-IV, and/or group-V atoms comprise carbon and/or germanium atoms. 
     
     
         19 . The integrated circuit of  claim 17 , wherein, in each first semiconductor region, a concentration of the group-III, group-IV, and/or group-V atoms is at a maximum level at an interface between the silicided portion and a non silicided portion. 
     
     
         20 . The integrated circuit of  claim 17 , further comprising other semiconductor regions each including a silicided portion having group-III, group-IV, and/or group-V atoms implanted therein. 
     
     
         21 . The integrated circuit of  claim 20 , wherein the group-III, group-IV, and/or group-V atoms of the other semiconductor regions comprise carbon and/or germanium atoms. 
     
     
         22 . The integrated circuit of  claim 20 , wherein the silicided portion of the first semiconductor regions is thicker than the silicided portion of the other semiconductor regions.