Thermally enhanced package to reduce thermal interaction between dies

Abstract

A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.

What is claimed is: 
     
         1 . A device comprising:
 plural integrated circuit (IC) chips attached to an upper surface of a substrate;   a lid over the IC chips; and   a slit through the lid at a boundary between adjacent IC chips.   
     
     
         2 . The device according to  claim 1 , wherein the IC chips comprise:
 a logic chip; and   at least one memory stack adjacent the logic chip.   
     
     
         3 . The device according to  claim 2 , wherein the slit is formed at a boundary between the logic chip and a memory stack. 
     
     
         4 . The device according to  claim 2 , wherein a slit is formed between the logic chip and each memory stack. 
     
     
         5 . The device according to  claim 1 , further comprising a heat sink over the lid. 
     
     
         6 . The device according to  claim 5 , further comprising at least one vertical heat pipe through the heat sink and the lid, down to the IC chips. 
     
     
         7 . The device according to  claim 6 , wherein each vertical heat pipe is in direct thermal contact with an IC chip and the heat sink. 
     
     
         8 . The device according to  claim 7 , further comprising a first thermal interface material (TIM 1 ) between the lid and the IC chips. 
     
     
         9 . The device according to  claim 8 , further comprising a second thermal interface material (TIM 2 ) between the heat sink and the lid. 
     
     
         10 . The device according to  claim 9 , wherein a length of the vertical heat pipes equals a sum of a thickness of TIM 1 , a thickness of the lid, a thickness of TIM 2 , and a height of the heat sink. 
     
     
         11 . The device according to  claim 7 , wherein the vertical heat pipes comprise copper (Cu). 
     
     
         12 . The device according to  claim 7 , wherein a diameter of each vertical heat pipe ranges from 1 millimeter (mm) to a width of the IC chip with which it is in thermal contact. 
     
     
         13 . The device according to  claim 7 , wherein the vertical heat pipes have conductivity in only one direction. 
     
     
         14 . A device comprising:
 plural integrated circuit (IC) chips attached to an upper surface of a substrate, wherein the IC chips comprise a logic chip and at least one memory stack adjacent the logic chip;   a lid over the IC chips;   a slit through the lid at a boundary between the logic chip and each memory stack; and   a heat sink over the lid.   
     
     
         15 . The device according to  claim 14 , further comprising at least one vertical heat pipe through the heat sink and the lid, down to the IC chips. 
     
     
         16 . The device according to  claim 15 , wherein each vertical heat pipe is in direct thermal contact with an IC chip and the heat sink. 
     
     
         17 . The device according to  claim 16 , further comprising a first thermal interface material (TIM 1 ) between the lid and the IC chips. 
     
     
         18 . The device according to  claim 17 , further comprising a second thermal interface material (TIM 2 ) between the heat sink and the lid. 
     
     
         19 . The device according to  claim 18 , wherein a length of the vertical heat pipes equals a sum of a thickness of TIM 1 , a thickness of the lid, a thickness of TIM 2 , and a height of the heat sink. 
     
     
         20 . The device according to  claim 15 , wherein each vertical heat pipe comprise copper (Cu).